參數資料
型號: AGLE600V2-FFG484C
元件分類: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA484
封裝: 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁數: 76/156頁
文件大?。?/td> 5023K
代理商: AGLE600V2-FFG484C
IGLOOe DC and Switching Characteristics
2- 12
Advance v0.3
Table 2-16 Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices
For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Definition
Device-Specific Dynamic
Contributions (W/MHz)
AGLE600
AGLE3000
PAC1
Clock contribution of a Global Rib
12.61
8.17
PAC2
Clock contribution of a Global Spine
2.66
1.18
PAC3
Clock contribution of a VersaTile row
0.56
PAC4
Clock contribution of a VersaTile used as a sequential module
0.071
PAC5
First contribution of a VersaTile used as a sequential module
0.045
PAC6
Second contribution of a VersaTile used as a sequential module
0.186
PAC7
Contribution of a VersaTile used as a combinatorial module
0.109
PAC8
Average contribution of a routing net
0.449
PAC9
Contribution of an I/O input pin (standard-dependent)
PAC10
Contribution of an I/O output pin (standard-dependent)
PAC11
Average contribution of a RAM block during a read operation
25.00
PAC12
Average contribution of a RAM block during a write operation
30.00
PAC13
Dynamic PLL contribution
2.10
* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or
SmartPower in Actel Libero IDE software.
Table 2-17 Different Components Contributing to the Static Power Consumption in IGLOO Devices
For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Definition
Device Specific Static Power (mW)
AGLE600
AGLE3000
PDC1
Array static power in Active mode
PDC2
Array static power in Static (Idle) mode
PDC3
Array static power in Flash*Freeze mode
PDC4
Static PLL contribution
0.90
PDC5
Bank quiescent power (VCCI-dependent)
PDC6
I/O input pin static power (standard-dependent)
PDC7
I/O output pin static power (standard-dependent)
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