參數(shù)資料
型號: AGLE600V2-FFG484C
元件分類: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA484
封裝: 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁數(shù): 85/156頁
文件大?。?/td> 5023K
代理商: AGLE600V2-FFG484C
IGLOOe DC and Switching Characteristics
2- 20
Advance v0.3
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-20 Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions
I/O Standard
Drive
Strength Slew Rate
VIL
VIH
VOL
VOH
IOL
1 I
OH
1
Min., V
Max., V
Min., V
Max., V
Min., V
mA mA
3.3 V LVTTL /
3.3 V LVCMOS
12 mA
High
–0.3
0.8
2
3.6
0.4
2.4
12
2.5 V LVCMOS
12 mA
High
–0.3
0.7
1.7
2.7
0.7
1.7
12
1.8 V LVCMOS
12 mA
High
–0.3
0.35 * VCCI 0.65*VCCI
1.9
0.45
VCCI – 0.45 12 12
1.5 V LVCMOS
12 mA
High
–0.3
0.35 * VCCI 0.65*VCCI
1.575
0.25 * VCCI 0.75 * VCCI 12 12
1.2 V LVCMOS4
2 mA
High
–0.3
0.35 * VCCI 0.65 * VCCI
1.26
0.25 * VCCI 0.75 * VCCI 22
3.3 V PCI
Per PCI Specification
3.3 V PCI-X
Per PCI-X Specification
3.3 V GTL
25 mA2
High
–0.3
VREF – 0.05 VREF + 0.05
3.6
0.4
25
2.5 V GTL
25 mA2
High
–0.3
VREF – 0.05 VREF + 0.05
2.7
0.4
25
3.3 V GTL+
35 mA
High
–0.3
VREF – 0.1 VREF + 0.1
3.6
0.6
35
2.5 V GTL+
33 mA
High
–0.3
VREF – 0.1 VREF + 0.1
2.7
0.6
33
HSTL (I)
8 mA
High
–0.3
VREF – 0.1 VREF + 0.1 1.575
0.4
VCCI – 0.4
8
HSTL (II)
15 mA2
High
–0.3
VREF – 0.1 VREF + 0.1 1.575
0.4
VCCI – 0.4
15
SSTL2 (I)
15 mA
High
–0.3
VREF – 0.2 VREF + 0.2
2.7
0.54
VCCI – 0.62 15 15
SSTL2 (II)
18 mA
High
–0.3
VREF – 0.2 VREF + 0.2
2.7
0.35
VCCI – 0.43 18 18
SSTL3 (I)
14 mA
High
–0.3
VREF – 0.2 VREF + 0.2
3.6
0.7
VCCI – 1.1 14 14
SSTL3 (II)
21 mA
High
–0.3
VREF – 0.2 VREF + 0.2
3.6
0.5
VCCI – 0.9 21 21
Notes:
1. Currents are measured at 85°C junction temperature.
2. Output drive strength is below JEDEC specification.
3. Output Slew Rates can be extracted from IBIS Models, located at
4. Applicable to V2 Devices ONLY, operating in the 1.2 V core range.
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