參數(shù)資料
型號: AGLE600V2-FG256C
元件分類: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA256
封裝: 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256
文件頁數(shù): 98/156頁
文件大?。?/td> 5023K
代理商: AGLE600V2-FG256C
IGLOOe DC and Switching Characteristics
2- 32
Advance v0.3
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.
Table 2-39 Minimum and Maximum DC Input and Output Levels
2.5 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL
IIH
Drive
Strength
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2
4 mA
–0.3
0.7
1.7
2.7
0.7
1.7
4
16
18
10
8 mA
–0.3
0.7
1.7
2.7
0.7
1.7
8
32
37
10
12 mA
–0.3
0.7
1.7
2.7
0.7
1.7
12
65
74
10
16 mA
–0.3
0.7
1.7
2.7
0.7
1.7
16
83
87
10
24 mA
–0.3
0.7
1.7
2.7
0.7
1.7
24
169
124
10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Figure 2-8 AC Loading
Table 2-40 AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point*
(V)
VREF (typ.) (V)
CLOAD (pF)
02.5
1.2
5
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Test Point
Enable Path
Datapath
35 pF
R = 1 k
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
相關(guān)PDF資料
PDF描述
AGLE600V2-FGG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V2-FGG484C FPGA, 13824 CLBS, 600000 GATES, PBGA256
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