2-4 Revision 13 JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O be" />
參數(shù)資料
型號(hào)： AGLE600V2-FG484I
廠商： Microsemi SoC
文件頁數(shù)： 77/166頁
文件大小： 0K
描述： IC FPGA 1KB FLASH 600K 484-FBGA
標(biāo)準(zhǔn)包裝： 60
系列： IGLOOe
邏輯元件/單元數(shù)： 13824
RAM 位總計(jì)： 110592
輸入/輸出數(shù)： 270
門數(shù)： 600000
電源電壓： 1.14 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
IGLOOe DC and Switching Characteristics
2-4
Revision 13
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup
behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 2-
2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±
0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the
"Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the IGLOOe FPGA Fabric User’s
Guide for information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
Output buffers, after 200 ns delay from input buffer activation.
Figure 2-1 V5 – I/O State as a Function of VCCI and VCC Voltage Levels
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCC
VCC = 1.425 V
Region 1: I/O Buffers are OFF
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
Activation trip point:
Va = 0.9 V ± 0.3 V
Deactivation trip point:
Vd = 0.8 V ± 0.3 V
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCCI
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
VCC = VCCI + VT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGLE600V2-FG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V2-FG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V2-FG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V2-FG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V2-FGG256 功能描述:IC FPGA 1KB FLASH 600K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
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