Revision 17 2-65 Table 2-90 AGLN020 Global Resource Commercial-Case Conditions: T" />
參數(shù)資料
型號: AGLN030V5-ZUCG81I
廠商: Microsemi SoC
文件頁數(shù): 131/150頁
文件大?。?/td> 0K
描述: IC FPGA NANO 1KB 30K 81-UCSP
標準包裝: 490
系列: IGLOO nano
邏輯元件/單元數(shù): 768
輸入/輸出數(shù): 66
門數(shù): 30000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-WFBGA,CSBGA
供應(yīng)商設(shè)備封裝: 81-UCSP(4x4)
IGLOO nano Low Power Flash FPGAs
Revision 17
2-65
Table 2-90 AGLN020 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.21
1.55
ns
tRCKH
Input High Delay for Global Clock
1.23
1.65
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
1.40
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
1.65
ns
tRCKSW
Maximum Skew for Global Clock
0.42
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-91 AGLN060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.32
1.62
ns
tRCKH
Input High Delay for Global Clock
1.34
1.71
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
1.40
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
1.65
ns
tRCKSW
Maximum Skew for Global Clock
0.38
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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