Revision 17 2-65 Table 2-90 AGLN020 Global Resource Commercial-Case Conditions: T" />
參數資料
型號： AGLN125V5-CSG81
廠商： Microsemi SoC
文件頁數： 131/150頁
文件大?。?/td> 0K
描述： IC FPGA NANO 1KB 125K 81-CSP
標準包裝： 640
系列： IGLOO nano
邏輯元件/單元數： 3072
RAM 位總計： 36864
輸入/輸出數： 60
門數： 125000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -20°C ~ 70°C
封裝/外殼： 81-WFBGA，CSBGA
供應商設備封裝： 81-CSP（5x5）
IGLOO nano Low Power Flash FPGAs
Revision 17
2-65
Table 2-90 AGLN020 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.21
1.55
ns
tRCKH
Input High Delay for Global Clock
1.23
1.65
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
1.40
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
1.65
ns
tRCKSW
Maximum Skew for Global Clock
0.42
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-91 AGLN060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.32
1.62
ns
tRCKH
Input High Delay for Global Clock
1.34
1.71
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
1.40
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
1.65
ns
tRCKSW
Maximum Skew for Global Clock
0.38
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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相關代理商/技術參數
參數描述
AGLN125V5-CSG81I 功能描述:IC FPGA NANO 1KB 125K 81-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:IGLOO nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數:- 邏輯元件/單元數:792 RAM 位總計:- 輸入/輸出數:120 門數:30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14）
AGLN125V5-DIELOT 制造商:Microsemi Corporation 功能描述:AGLN125V5-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film
AGLN125V5-QNG100 制造商:Microsemi Corporation 功能描述:FPGA IGLOO NANO FAMILY 125K GATES 130NM (CMOS) TECHNOLOGY 1. - Trays
AGLN125V5-QNG100I 制造商:Microsemi Corporation 功能描述:FPGA IGLOO NANO FAMILY 125K GATES 130NM (CMOS) TECHNOLOGY 1. - Trays
AGLN125V5-VQ100 功能描述:IC FPGA NANO 1KB 125K 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:IGLOO nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數:- 邏輯元件/單元數:792 RAM 位總計:- 輸入/輸出數:120 門數:30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14）
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