Revision 17 2-63 Global Resource Characteristics AGLN125 Clock Tree Topology Clock delays are device-specific. Fi" />
參數(shù)資料
型號(hào): AGLN250V5-CSG81
廠商: Microsemi SoC
文件頁數(shù): 128/150頁
文件大?。?/td> 0K
描述: IC FPGA NANO 1KB 250K 81-CSP
標(biāo)準(zhǔn)包裝: 640
系列: IGLOO nano
邏輯元件/單元數(shù): 6144
RAM 位總計(jì): 36864
輸入/輸出數(shù): 60
門數(shù): 250000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -20°C ~ 70°C
封裝/外殼: 81-WFBGA,CSBGA
供應(yīng)商設(shè)備封裝: 81-CSP(5x5)
IGLOO nano Low Power Flash FPGAs
Revision 17
2-63
Global Resource Characteristics
AGLN125 Clock Tree Topology
Clock delays are device-specific. Figure 2-25 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-25 is driven by a CCC located on the west side of the AGLN125 device.
It is used to drive all D-flip-flops in the device.
Figure 2-25 Example of Global Tree Use in an AGLN125 Device for Clock Routing
Central
Global Rib
VersaTile
Rows
Global Spine
CCC
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