參數資料
| 型號： | AGLP030V2-VQ128 |
| 廠商： | Microsemi SoC |
| 文件頁數： | 32/134頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA IGLOO PLUS 30K 128-VQFN |
| 標準包裝： | 90 |
| 系列： | IGLOO PLUS |
| 邏輯元件/單元數： | 792 |
| 輸入/輸出數： | 101 |
| 門數： | 30000 |
| 電源電壓： | 1.14 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 128-TQFP |
| 供應商設備封裝： | 128-VTQFP（14x14） |
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Revision 16
5-1
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the IGLOO PLUS datasheet.
Revision
Changes
Page
Revision 16
(December 2012)
The "IGLOO PLUS Ordering Information" section has been updated to mention "Y"
as "Blank" mentioning "Device Does Not Include License to Implement IP Based on
the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43175).
The note in Table 2-90 IGLOO PLUS CCC/PLL Specification and Table 2-91
IGLOO PLUS CCC/PLL Specification referring the reader to SmartGen was revised
to refer instead to the online help associated with the core (SAR 42566).
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
NA
Revision 15
(October 2012)
Values updated for IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage in
IGLOO PLUS Devices and for IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
in IGLOO PLUS Devices (SAR 31988). Also added a new Note to the two tables.
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip
(SoC) throughout the document (SAR 40277).
N/A
Revision 14
(September 2012)
The "Security" section was modified to clarify that Microsemi does not support read-
back of programmed data.
Revision 13
(June 2012)
Figure 2-30 FIFO Read and Figure 2-31 FIFO Write have been added (SAR
34843).
Updated the terminology used in Timing Characteristics in the following tables:
Table 2-96 FIFO and Table 2-97 FIFO (SAR 38236).
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"
section in the "Pin Descriptions and Packaging" section: "Within the package, the
VMV plane is decoupled from the simultaneous switching noise originating from the
output buffer VCCI domain" and replaced with “Within the package, the VMV plane
biases the input stage of the I/Os in the I/O banks” (SAR 38320). The datasheet
mentions that "VMV pins must be connected to the corresponding VCCI pins" for an
ESD enhancement.
Revision 12
(March 2012)
were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in the
industry (SAR 34664).
The Y security option and Licensed DPA Logo were added to the "IGLOO PLUS
Ordering Information" section. The trademarked Licensed DPA Logo identifies that a
product is covered by a DPA counter-measures license from Cryptography Research
(SAR 34724).
The "Specifying I/O States During Programming" section is new (SAR 34695).
The following sentence was removed from the "Advanced Architecture" section:
"In addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOO PLUS devices via an IEEE 1532 JTAG interface"
(SAR 34684).
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| AGLP030V2-VQG128 | IC FPGA IGLOO PLUS 30K 128-VQFN |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AGLP030V2-VQ128I | 功能描述:IC FPGA IGLOO PLUS 30K 128-VQFN RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:IGLOO PLUS 標準包裝:152 系列:IGLOO PLUS LAB/CLB數:- 邏輯元件/單元數:792 RAM 位總計:- 輸入/輸出數:120 門數:30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14） |
| AGLP030-V2VQ289 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP030-V2VQ289ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP030-V2VQ289I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP030-V2VQ289PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
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