參數(shù)資料
型號： AGLP060V2-CS289I
元件分類： FPGA
英文描述： FPGA, 1584 CLBS, 60000 GATES, PBGA289
封裝： 14 X 14 MM , 1.2 MM HEIGHT, 0.8 MM PITCH, CSP-289
文件頁數(shù)： 100/128頁
文件大小： 4383K
代理商： AGLP060V2-CS289I
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 59
1.2 V DC Core Voltage
Table 2-86 AGLP125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.36
1.71
ns
tRCKH
Input High Delay for Global Clock
1.39
1.82
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.43
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-87 AGLP030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.80
2.09
ns
tRCKH
Input High Delay for Global Clock
1.88
2.27
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.39
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
相關(guān)PDF資料
PDF描述
AGLP060V2-CS289 FPGA, 1584 CLBS, 60000 GATES, PBGA289
AGLP060V2-CSG201I FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V2-CSG201 FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V2-CSG289I FPGA, 1584 CLBS, 60000 GATES, PBGA289
AGLP060V2-CSG289 FPGA, 1584 CLBS, 60000 GATES, PBGA289
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGLP060-V2CS289PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP060V2-CSG201 功能描述:IC FPGA IGLOO PLUS 60K 201-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
AGLP060V2-CSG201I 功能描述:IC FPGA IGLOO PLUS 60K 201-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
AGLP060-V2CSG289 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP060V2-CSG289 功能描述:IC FPGA IGLOO PLUS 60K 289-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
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