參數(shù)資料
型號: AGLP060V2-CS289I
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PBGA289
封裝: 14 X 14 MM , 1.2 MM HEIGHT, 0.8 MM PITCH, CSP-289
文件頁數(shù): 13/128頁
文件大?。?/td> 4383K
代理商: AGLP060V2-CS289I
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
1-5
VersaTiles
The IGLOO PLUS core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS
core tiles. The IGLOO PLUS VersaTile supports the following:
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
User Nonvolatile FlashROM
Actel IGLOO PLUS devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The
FlashROM can be used in diverse system applications:
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard IGLOO PLUS IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks (except in AGLP030 devices), as in security keys
stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The Actel IGLOO PLUS development software solutions, Libero Integrated Design Environment (IDE)
and Designer, have extensive support for the FlashROM. One such feature is auto-generation of
sequential programming files for applications requiring a unique serial number in each part. Another
feature allows the inclusion of static data for system version control. Data for the FlashROM can be
generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive
programming file support is also included to allow for easy programming of large numbers of parts with
differing FlashROM contents.
Figure 1-3
VersaTile Configurations
X1
Y
X2
X3
LUT-3
Data
Y
CLK
Enable
CLR
D-FF
Data
Y
CLK
CLR
D-FF
LUT-3 Equivalent
D-Flip-Flop with Clear or Set
Enable D-Flip-Flop with Clear or Set
相關(guān)PDF資料
PDF描述
AGLP060V2-CS289 FPGA, 1584 CLBS, 60000 GATES, PBGA289
AGLP060V2-CSG201I FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V2-CSG201 FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V2-CSG289I FPGA, 1584 CLBS, 60000 GATES, PBGA289
AGLP060V2-CSG289 FPGA, 1584 CLBS, 60000 GATES, PBGA289
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AGLP060V2-CSG201I 功能描述:IC FPGA IGLOO PLUS 60K 201-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)
AGLP060-V2CSG289 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP060V2-CSG289 功能描述:IC FPGA IGLOO PLUS 60K 289-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)