參數(shù)資料
型號: AGLP060V2-CSG201
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PBGA201
封裝: 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-201
文件頁數(shù): 51/128頁
文件大?。?/td> 4383K
代理商: AGLP060V2-CSG201
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 15
User I/O Characteristics
Timing Model
Figure 2-3
Timing Model
Operating Conditions: STD Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices
DQ
Y
DQ
Y
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVCMOS 2.5 V Output Drive
Strength = 12 mA High Slew Rate
Input LVCMOS 2.5 V
LVCMOS 1.5 V
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTLOutput drive strength = 8 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5 V Output drive strength = 4 mA
High slew rate
LVTTLOutput drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL
Clock
Input LVTTL
Clock
Input LVTTL
Clock
tPD = 1.40 ns
tPD = 0.89 ns
tDP = 1.62 ns
tPD = 1.98 ns
tDP = 1.62 ns
tPD = 1.24 ns
tDP = 1.70 ns
tPD = 0.86 ns
tDP = 2.07 ns
tPD = 0.87 ns
tPY = 0.85 ns
tCLKQ = 0.80 ns
tOCLKQ = 0.89 ns
tSUD = 0.84 ns
tOSUD = 0.18 ns
tDP = 1.62 ns
tPY = 0.85 ns
tPY = 1.15 ns
tCLKQ = 0.80 ns
tSUD = 0.84 ns
tPY = 0.85 ns
tICLKQ = 0.63 ns
tISUD = 0.18 ns
tPY = 1.06 ns
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