參數(shù)資料
型號: AGLP060V2-CSG201
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PBGA201
封裝: 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-201
文件頁數(shù): 93/128頁
文件大小: 4383K
代理商: AGLP060V2-CSG201
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 53
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Table 2-80 Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
Equation
Parameter
Std.
Units
INV
Y = !A
tPD
0.72
ns
AND2
Y = A B
tPD
0.86
ns
NAND2
Y = !(A B)
tPD
1.00
ns
OR2
Y = A + B
tPD
1.26
ns
NOR2
Y = !(A + B)
tPD
1.16
ns
XOR2
Y = A
Bt
PD
1.46
ns
MAJ3
Y = MAJ(A, B, C)
tPD
1.47
ns
XOR3
Y = A
B Ct
PD
2.12
ns
MUX2
Y = A !S + B S
tPD
1.24
ns
AND3
Y = A B C
tPD
1.40
ns
Note:
For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-81 Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Combinatorial Cell
Equation
Parameter
Std.
Units
INV
Y = !A
tPD
1.26
ns
AND2
Y = A B
tPD
1.46
ns
NAND2
Y = !(A B)
tPD
1.78
ns
OR2
Y = A + B
tPD
2.47
ns
NOR2
Y = !(A + B)
tPD
2.17
ns
XOR2
Y = A
Bt
PD
2.62
ns
MAJ3
Y = MAJ(A, B, C)
tPD
2.66
ns
XOR3
Y = A
B Ct
PD
3.77
ns
MUX2
Y = A !S + B S
tPD
2.20
ns
AND3
Y = A B C
tPD
2.49
ns
Note:
For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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