- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄294984 > AGLP060V2-CSG289 FPGA, 1584 CLBS, 60000 GATES, PBGA289 PDF資料下載
參數(shù)資料
| 型號(hào)： | AGLP060V2-CSG289 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1584 CLBS, 60000 GATES, PBGA289 |
| 封裝： | 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289 |
| 文件頁(yè)數(shù)： | 102/128頁(yè) |
| 文件大?。?/td> | 4383K |
| 代理商： | AGLP060V2-CSG289 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)當(dāng)前第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 61
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-90 IGLOO PLUS CCC/PLL Specification
For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage
Parameter
Min.
Typ.
Max.
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
250
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
250
MHz
Delay Increments in Programmable Delay Blocks 1, 2
360
ps
Number of Programmable Values in Each Programmable Delay Block
32
Serial Clock (SCLK) for Dynamic PLL3,4
Input Cycle-to-Cycle Jitter (peak magnitude)
100
MHz
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter5
LockControl = 0
2.5
LockControl = 1
1.5
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 1 1, 2
1.25
15.65
ns
Delay Range in Block: Programmable Delay 2 1, 2
0.469
15.65
ns
Delay Range in Block: Fixed Delay 1, 2
3.5
ns
VCO Output Peak-to-Peak Period Jitter FCCC_OUT
6
Maximum Peak-to-Peak Period Jitter6,7,8
SSO
≤ 2 SSO ≤ 4
SSO
≤ 8
SSO
≤ 16
0.75 MHz to 50 MHz
0.50%
0.60%
0.80%
1.20%
50 MHz to 250 MHz
2.50%
4.00%
6.00%
12.00%
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings.
2. TJ = 25°C, VCC = 1.5 V
3. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions. For specific junction
temperature and voltage supply, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values.
4. The AGLP030 device does not support a PLL.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider
settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output
divider settings.
7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate, VCC/VCCPLL = 1.14 V,
VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load.
8. SSO are outputs that are synchronous to a single clock domain and have clock-to-out times that are within ±200 ps of
each other.Switching I/Os are placed outside of the PLL bank. Refer to the "ProASIC3/E SSO and Pin Placement
Guidelines" chapter of the ProASIC3 FPGA Fabric User’s Guide.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGLP060V2-VQ176I | FPGA, 1584 CLBS, 60000 GATES, PQFP176 |
| AGLP060V2-VQ176 | FPGA, 1584 CLBS, 60000 GATES, PQFP176 |
| AGLP060V2-VQG176I | FPGA, 1584 CLBS, 60000 GATES, PQFP176 |
| AGLP060V2-VQG176 | FPGA, 1584 CLBS, 60000 GATES, PQFP176 |
| AGLP060V2CS201I | FPGA, 1584 CLBS, 60000 GATES, PBGA201 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLP060-V2CSG289ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP060-V2CSG289I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP060V2-CSG289I | 功能描述:IC FPGA IGLOO PLUS 60K 289-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| AGLP060-V2CSG289PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP060-V2FCS289 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。