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參數(shù)資料
| 型號(hào)： | AGLP060V5-CSG289I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1584 CLBS, 60000 GATES, PBGA289 |
| 封裝： | 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289 |
| 文件頁數(shù)： | 2/128頁 |
| 文件大?。?/td> | 4383K |
| 代理商： | AGLP060V5-CSG289I |
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IGLOO PLUS Device Family Overview
1- 4
R ev isio n 1 1
Flash*Freeze Technology
The IGLOO PLUS device has an ultra-low power static mode, called Flash*Freeze mode, which retains
all SRAM and register information and can still quickly return to normal operation. Flash*Freeze
technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global
I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be
driven or can be toggling without impact on power consumption, and the device retains all core registers,
SRAM information, and I/O states. I/Os can be individually configured to either hold their previous state
or be tristated during Flash*Freeze mode. Alternatively, they can be set to a certain state using weak pull-
up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins,
or PLL, and the device consumes as little as 5 W in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when it is safe to transition to this mode. Refer to Figure 1-2 for an illustration of entering/exiting
Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode
usage is not planned.
* Not supported by AGLP030 devices
Figure 1-1
IGLOO PLUS Device Architecture Overview with Four I/O Banks (AGLP030, AGLP060, and
AGLP125)
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
VersaTile
CCC
I/Os
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 0
Bank
1
Bank
1
Bank
3
Bank
3
Bank 2
*
Figure 1-2
IGLOO PLUS Flash*Freeze Mode
Actel
IGLOO PLUS
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGLP060V5-CSG289 | FPGA, 1584 CLBS, 60000 GATES, PBGA289 |
| AGLP060V5-VQ176I | FPGA, 1584 CLBS, 60000 GATES, PQFP176 |
| AGLP060V5-VQ176 | FPGA, 1584 CLBS, 60000 GATES, PQFP176 |
| AGLP060V5-VQG176I | FPGA, 1584 CLBS, 60000 GATES, PQFP176 |
| AGLP060V5-VQG176 | FPGA, 1584 CLBS, 60000 GATES, PQFP176 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLP060-V5CSG289PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP060-V5FCS289 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP060V5-FCS289 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOO PLUS 60K GATES 512 CELLS 130NM 1.5V 289CSP - Trays |
| AGLP060-V5FCS289ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP060-V5FCS289I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
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