參數(shù)資料
型號： AGLP060V5-CSG289I
元件分類： FPGA
英文描述： FPGA, 1584 CLBS, 60000 GATES, PBGA289
封裝： 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289
文件頁數(shù)： 49/128頁
文件大?。?/td> 4383K
代理商： AGLP060V5-CSG289I
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 13
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—PS-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
FCLK is the global clock signal frequency.
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.
β
1 is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-14.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β
2 is the RAM enable rate for read operations.
FWRITE-CLOCK is the memory write clock frequency.
β
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on
PLL Contribution—PPLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.
1
相關(guān)PDF資料
PDF描述
AGLP060V5-CSG289 FPGA, 1584 CLBS, 60000 GATES, PBGA289
AGLP060V5-VQ176I FPGA, 1584 CLBS, 60000 GATES, PQFP176
AGLP060V5-VQ176 FPGA, 1584 CLBS, 60000 GATES, PQFP176
AGLP060V5-VQG176I FPGA, 1584 CLBS, 60000 GATES, PQFP176
AGLP060V5-VQG176 FPGA, 1584 CLBS, 60000 GATES, PQFP176
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGLP060-V5CSG289PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP060-V5FCS289 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP060V5-FCS289 制造商:Microsemi Corporation 功能描述:FPGA IGLOO PLUS 60K GATES 512 CELLS 130NM 1.5V 289CSP - Trays
AGLP060-V5FCS289ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP060-V5FCS289I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
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