參數(shù)資料
型號: AGLP060V5-VQ176
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PQFP176
封裝: 20 X 20 MM, 1 MM HEIGHT, 0.4 MM PITCH, ROHS COMPLIANT, VQFP-176
文件頁數(shù): 116/128頁
文件大?。?/td> 4383K
代理商: AGLP060V5-VQ176
IGLOO PLUS DC and Switching Characteristics
2- 74
R e v i sio n 1 1
Figure 2-33 FIFO FULL Flag and AFULL Flag Assertion
Figure 2-34 FIFO EMPTY Flag and AEMPTY Flag Deassertion
Figure 2-35 FIFO FULL Flag and AFULL Flag Deassertion
NO MATCH
Dist = AFF_TH
MATCH (FULL)
tCKAF
tWCKFF
tCYC
WCLK
FULL
AFULL
WA/RA
(Address Counter)
WCLK
WA/RA
(Address Counter)
MATCH
(EMPTY)
NO MATCH
Dist = AEF_TH + 1
NO MATCH
RCLK
EMPTY
1st Rising
Edge
After 1st
Write
2nd Rising
Edge
After 1st
Write
tRCKEF
tCKAF
AEMPTY
Dist = AFF_TH – 1
MATCH (FULL)
NO MATCH
tWCKF
tCKAF
1st Rising
Edge
After 1st
Read
1st Rising
Edge
After 2nd
Read
RCLK
WA/RA
(Address Counter)
WCLK
FULL
AFULL
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