參數(shù)資料
型號: AGLP060V5-VQ176
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PQFP176
封裝: 20 X 20 MM, 1 MM HEIGHT, 0.4 MM PITCH, ROHS COMPLIANT, VQFP-176
文件頁數(shù): 75/128頁
文件大?。?/td> 4383K
代理商: AGLP060V5-VQ176
IGLOO PLUS DC and Switching Characteristics
2- 36
R e v i sio n 1 1
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-58 Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH
IIL
1 I
IH
2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
2 mA
–0.3
0.35 * VCCI
0.7 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
2
13
16
10
4 mA
–0.3
0.35 * VCCI
0.7 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
4
25
33
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-10 AC Loading
Table 2-59 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
01.5
0.75
5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
Test Point
Enable Path
Datapath
5 pF
R = 1 k
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
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