參數(shù)資料
型號: AGLP125V5-CSG281I
元件分類: FPGA
英文描述: FPGA, 3120 CLBS, 125000 GATES, PBGA281
封裝: 10 X 10 MM, 1.05 MM HEIGHT, 0.5 MM PITCH, ROHS COMPLIANT, CSP-281
文件頁數(shù): 58/128頁
文件大?。?/td> 4383K
代理商: AGLP125V5-CSG281I
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 21
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-23 Summary of AC Measuring Points
Standard
Measuring Trip Point (Vtrip)
3.3 V LVTTL / 3.3 V LVCMOS
1.4 V
3.3 V LVCMOS Wide Range
1.4 V
2.5 V LVCMOS
1.2 V
1.8 V LVCMOS
0.90 V
1.5 V LVCMOS
0.75 V
1.2 V LVCMOS
0.60 V
1.2 V LVCMOS Wide Range
0.60 V
Table 2-24 I/O AC Parameter Definitions
Parameter
Parameter Definition
tDP
Data to Pad delay through the Output Buffer
tPY
Pad to Data delay through the Input Buffer
tDOUT
Data to Output Buffer delay through the I/O interface
tEOUT
Enable to Output Buffer Tristate Control delay through the I/O interface
tDIN
Input Buffer to Data delay through the I/O interface
tHZ
Enable to Pad delay through the Output Buffer—High to Z
tZH
Enable to Pad delay through the Output Buffer—Z to High
tLZ
Enable to Pad delay through the Output Buffer—Low to Z
tZL
Enable to Pad delay through the Output Buffer—Z to Low
tZHS
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
相關PDF資料
PDF描述
AGLP125V5-CSG281 FPGA, 3120 CLBS, 125000 GATES, PBGA281
AGLP125V5-CSG289I FPGA, 3120 CLBS, 125000 GATES, PBGA289
AGLP125V5-CSG289 FPGA, 3120 CLBS, 125000 GATES, PBGA289
AGLP125V5CS281I FPGA, 3120 CLBS, 125000 GATES, PBGA281
AGLP125V5CS281 FPGA, 3120 CLBS, 125000 GATES, PBGA281
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