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參數(shù)資料
| 型號： | AK2548A |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 28/31頁 |
| 文件大小： | 171K |
| 代理商： | AK2548A |
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ASAHI K ASEI [AK2548A]
MS0021-E-00 2000/7
28
SERIAL INTERFACE
The timing of serial interface is shown below. SDO pin is fixed to High-Z except data output timing.
A7-A4 is “don’t care”.
When CS=”0”, consecutive data write is available.
In data write mode, input data is set to the internal register at the 16th falling edge of the SCLK.
If CS is set to high before the 16th falling edge of the SCLK, the write data is canceled.
If CS is set to high before the 8bits read data is output completely, the read data is fixed High-Z
after that.
R/W=1: read
R/W=0: write
HARDWARE INTERFACE
In hardware mode, the control of loopback, TAOS, LOSAIS, RDEN are not available.
The fixed data of the channel control register is shown below.
When the loss of MCLK is detected, INT_LOMC goes to High.
Channel Control Register(Fixed data in hardware mode)
TAOSx
(0)
Note 1)
(0)
LOSAISx
(0)
E Cx
RLOOPx
LLOOPx
(0)
POLNx
Note 3)
MSKx
(invalid)
PDx
Note 2)
Note 1) can be controlled all channel together by the EC pin.
Note 2) can be controlled all channel together by the PD pin.
Note 3) Please refer to OUTPUT CONTROL.
R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
CS
SCLK
SDI
SDO
High-Z
1
16
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