參數(shù)資料
型號(hào)： AK4529VQ
英文描述： Converter IC
中文描述： 轉(zhuǎn)換器IC
文件頁(yè)數(shù)： 6/38頁(yè)
文件大小： 382K
代理商： AK4529VQ
ASAHI KASEI
[AK4529]
MS0082-E-00
2001/3
- 6 -
No.
23
24
25
26
27
28
29
Pin Name
LOUT3
ROUT3
LOUT2
ROUT2
LOUT1
ROUT1
NC
I/O
O
O
O
O
O
O
-
Function
DAC3 Lch Analog Output Pin
DAC3 Rch Analog Output Pin
DAC2 Lch Analog Output Pin
DAC2 Rch Analog Output Pin
DAC1 Lch Analog Output Pin
DAC1 Rch Analog Output Pin
No Connect
No internal bonding.
No Connect
No internal bonding.
Lch Analog Input Pin
Rch Analog Input Pin
Zero Input Detect 2 Pin (Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”.
Analog Input Overflow Detect Pin (Note 3)
This pin goes to “H” if the analog input of Lch or Rch is overflows.
Common Voltage Output Pin, AVDD/2
Large external capacitor around 2.2μF is used to reduce power-supply noise.
Positive Voltage Reference Input Pin, AVDD
Analog Power Supply Pin, 4.5V
～
5.5V
Analog Ground Pin, 0V
Zero Input Detect 1 Pin (Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”.
Master Clock Input Pin
Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
Audio Data Interface Format 0 Pin in parallel control mode
Chip Select Pin in 3-wire serial control mode
This pin should be connected to DVDD at I
2
C bus control mode
Audio Data Interface Format 1 Pin in parallel control mode
Control Data Clock Pin in serial control mode
I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I
2
C Bus)
Loopback Mode 0 Pin in parallel control mode
Enables digital loop-back from ADC to 4 DACs.
Control Data Input Pin in serial control mode
I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I
2
C Bus)
TDM I/F Format Mode Pin (Note 1)
“L”: Normal format, “H”: TDM format
30
NC
-
31
32
33
LIN
RIN
DZF2
I
I
O
OVF
O
34
VCOM
O
35
36
37
38
VREFH
AVDD
AVSS
DZF1
I
-
-
O
39
40
MCLK
P/S
I
I
DIF0
CSN
I
I
41
DIF1
SCL/CCLK
I
I
42
LOOP0
I
43
SDA/CDTI
I/O
44
TDM
I
Notes: 1. SDOS, SMUTE, DFS, and TDM pins are ORed with register data if P/S = “L”.
2. The group 1 and 2 can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L”.
3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode.
4. All input pins should not be left floating.
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