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參數(shù)資料
| 型號： | AK4641VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16 BIT CODEC WITH BLUETOOTH INTERFACE |
| 中文描述： | 16位編解碼器與藍牙接口 |
| 文件頁數(shù)： | 18/51頁 |
| 文件大小： | 461K |
| 代理商： | AK4641VN |
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ASAHI KASEI
[AK4641]
MS0301-E-00
2004/05
- 25 -
[3] Example of ALC1 Operation
Table 11 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB.
fs=8kHz
fs=16kHz
fs=44.1kHz
Register Name
Comment
Data
Operation
Data
Operation
Data
Operation
LMTH
Limiter detection Level
1
4dBFS
1
4dBFS
1
4dBFS
LTM1-0
Limiter operation period at ZELM = 1
00
Don’t use
00
Don’t use
00
Don’t use
ZELM
Limiter zero crossing detection
0
Enable
0
Enable
0
Enable
ZTM1-0
Zero crossing timeout period
00
16ms
01
16ms
10
11.6ms
WTM1-0
Recovery waiting period
*WTM1-0 bits should be the same data
as ZTM1-0 bits
00
16ms
01
16ms
10
11.6ms
REF6-0
Maximum gain at recovery operation
47H
+27.5dB
47H
+27.5dB
47H
+27.5dB
IPGA6-0
Gain of IPGA at ALC1 operation Start
10H
0dB
10H
0dB
10H
0dB
LMAT1-0
Limiter ATT Step
00
1 step
00
1 step
00
1 step
RATT
Recovery GAIN Step
0
1 step
0
1 step
0
1 step
ALC1
ALC1 Enable bit
1
Enable
1
Enable
1
Enable
Table 11. Example of the ALC1 setting
The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1
operation is finished by ALC1 bit = “0” or PMMIC bit = “0”.
LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
IPGA gain at ALC1 operation start can be changed from the default value of IPGA6-0 bits while PMMIC bit is “1” and
ALC1 bit is “0”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.
Manual Mode
* The value of IPGA should be
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (REF6-0)
WR (IPGA6-0)
ALC1 Operation
WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 1
Maximum Gain = +27.5dB
Limiter Detection Level =
4dBFS
(1) Addr=08H, Data=00H
(2) Addr=0AH, Data=47H
(4) Addr=09H, Data=21H
(3) Addr=0BH, Data=10H
* ALC1 bit must be set to “1” at more than zero cross time out period
after the value of IPGA is set (see figure 22).
Note : WR : Write
Figure 23. Registers set-up sequence at ALC1 operation
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