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參數(shù)資料
| 型號(hào)： | AK4665AEN |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, QFN-32 |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 522K |
| 代理商： | AK4665AEN |
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ASAHI KASEI
[AK4665A]
MS0440-E-01
2006/05
- 32 -
Headphone Output (HPL/HPR pins)
Power supply voltage for headphone amplifiers is applied from HVDD pin for the positive supply and the negative supply
generated by the internal charge pump circuit. The headphone amplifier is single-ended outputs and centered on 0V
(AVSS). Therefore, the capacitor for AC-coupling can be removed. The minimum load resistance is 16
. HPG bit set the
output voltage (Table 33).
HPG bit
Output Voltage
Output Power
0
1.5Vpp@0dBFS
17mW@16
Default
1
2.0Vpp@
3dBFS
31mW@16
Table 33. Headphone Output Voltage / Power
The headphone output is enabled when HPMTN bit is “1” and muted when HPMTN bit is “0”. The mute ON/OFF time
are set by PTS1-0 bits (Table 39) when MOFF8 bit is “0”. When MOFF8 bit is “1”, the ON/OFF is done immediately.
When PMHPL and PMHPR bits are “0”, the headphone amplifiers are powered-down completely. At that time, the HPL
and HPR pins are AVSS voltage. The power-up/down time are set by PUT1-0 bits (Table 38) when MOFF0 bit is “0”.
When MOFF0 bit is “1”, the power up/down is done immediately.
PMHPL/R bits
HPMTN bit
HP-Amp
0
x
Power-down
Default
0
Power-up & Mute
1
Power-up & Output
Table 34. Headphone output states
The ON/OFF of each path is set by DACHL, LINHL, MINHL, DACHR, RINHR and MINHR bits. The summation gain
of each path is 0dB (typ) at HPG bit = “0” and +5.5dB (typ) at HPG bit = “1”.
HPL/HP R pin
LIN/RIN pin
MIN pin
LINHL/RINHR bit
MINHL/MINHR bit
DACHL/DACHR bit
DACL/DACR
Figure 20. The Summation Circuit of Headphone Output
(L+R)/2 signal of DAC is output from HPL and HPR pins when HPM bit is “1”.
DACHL
HPM bit
HPL pin
0
x
Path OFF
Default
0
L
1
(L+R)/2
Table 35. Headphone Output Mode (Lch)
DACHR
HPM bit
HPR pin
0
x
Path OFF
Default
0
R
1
(L+R)/2
Table 36. Headphone Output Mode (Rch)
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