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參數(shù)資料
| 型號： | AK4665AEN |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, QFN-32 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 522K |
| 代理商： | AK4665AEN |
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ASAHI KASEI
[AK4665A]
MS0440-E-01
2006/05
- 36 -
2) ADC (Line In: in case of common jack with headphone)
Power Supply
Clock Input
PMADC bit
ADC Internal
State
AINL1/R1 pins
PD(Power-down)
Init Cycle
Normal Operation
(8) 2081/fs
SDTO pin
(9) GD
(7)
(5)
PD
(9) GD
(Hi-Z)
Don’t care
PMVCM bit
(1) >150ns
(6) >0
FS3-0, DFS bits
NVSS pin
(2) >0
(3) >0
(4) >0
0V
HVDD
Don’t care
0V
PDN pin
PMCP bit
XH, X
0H, 0
(10)
PMHPL/R bits
(11)
Figure 22. Power-up/down Sequence of ADC
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) FS3-0 and DFS bits should be set after PDN pin goes to “H”.
(3) PMVCM bit should be changed to “1” after FS3-0 and DFS bits are set.
(4) PMCP bit should be changed to “1” after PMVCM bit is changed to “1”. The charge pump circuit is powered-up and
NVSS pin goes to –HVDD voltage according to the setting of FS3-0 and DFS bits.
(5) External clocks (MCLK, BICK and LRCK) are needed to operate the charge pump circuit and ADC.
(6) PMADC bit should be changed to “1” after NVSS pin goes to –HVDD voltage.
(7) When PMADC bit is changed to “1”, AINL1/R1 pins are biased to VCOM voltage. Rising time constant is
determined by input capacitor for AC coupling and input resistance. In case of 1F input capacitor, time constant is
τ = 1F x 60k = 60ms (typ)
(8) The analog part of ADC is initialized during 2081/fs (=47ms@fs=44.1kHz) after exiting the power-down state.
SDTO is “L” at that time.
(9) Digital output corresponding to analog input has the group delay (GD) of 17/fs (=385s@fs=44.1kHz).
(10) When PMCP bit is changed to “0”, the charge pump circuit is powered-down and NVSS pin becomes 0V. Falling
time constant is determined by capacitor and internal resistance (typ 17.5k
). In case of 2.2F capacitor, time
constant is
τ = 2.2F x 17.5k = 38.5ms (typ)
(11) When PMHPL/R bits = “0”, HPL/R pins are connected to AVSS with internal pull-down resistance (typ 100k
).
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