參數(shù)資料
型號(hào)： AL2007LA
英文描述： Synchronous Push-Pull PWM Controllers; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +125°C
中文描述： AL2007LA為20MHz?170MHz的FSPLL AL2007LA |數(shù)據(jù)資料
文件頁(yè)數(shù)： 11/16頁(yè)
文件大小： 156K
代理商： AL2007LA
SEC ASIC
20MHZ~170MHZ FSPLL
ANALOG
11 / 16
AL2005H
NAME
PIN NO
I/O TYPE
PIN DESCRIPTION
VDD
2
DP
PLL Core Digital power supply
VSS
3
DG
PLL Core Digital ground
PWRDN
4
DI
FSPLL clock power down
-PWRDN is High, PLL do not operating under
this condition.
-If isn't used this pin, tied to VSS.
P0~P5
5~10
DI
6Bit Pre-Divider Input
VDDA
14
AP
PLL Core Analog power supply
VSSA
15
AG
PLL Core Analog ground
OSCDIS
16
DI
XTAL-OSC enable/disable control pin.
-OSCDIS is HIGH, PLL don't operating under
this condition.
-If isn't used this pin, tied to VSS
FIN/XTALIN
17
AI
External clock source input or crystal input
XTALOUT
18
AO
Crystal output
-If a crystal is used, it is connected across
the I/O pins XTALIN and XTALOUT.
If isn't used it has to float the output.
VSSAP
19
PG
Analog PAD ground
VDDAP
20
PP
Analog PAD supply power
VFOUT
21
DO
Fout Divided by 1/[3~65] output test pin.
FOUT
22
DO
20MHZ~170MHz clock output
FILTER
23
AO
Pump out is connected to the FILTER.
A 560pF Capcitor is connected between the
pin and analog pin
V0~V5
26~31
DI
VFOUT divide control pins.
-End users used not this pins, tied to VDD or VSS
VSSP
33
PG
Digital PAD ground
ACOUT
34
DO
Internal Dummy test block output
VDDP
35
PP
Digital PAD supply power
ACIN
36
DI
Internal Dummy test block input
Do not float this pin. must be tie to VDD or VSS
S0~S1
38~39
DI
2Bit Post scaler input
M0~M7
40~47
DI
8bit main divider input
RO
48
DO
Internal Dummy test block output
NOTE: NC means no connection.
PACKAGE PIN DESCRIPTION (48QFP)
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