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參數(shù)資料
| 型號： | AL2007LA |
| 英文描述： | Synchronous Push-Pull PWM Controllers; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +125°C |
| 中文描述： | AL2007LA為20MHz?170MHz的FSPLL AL2007LA |數(shù)據(jù)資料 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 156K |
| 代理商： | AL2007LA |
SEC ASIC
20MHZ~170MHZ FSPLL
ANALOG
5 / 16
AL2005H
Functional Description
A PLL is the circuit synchronizing an output signal (generated by a VCO) with a reference
or
input signal in frequency as well as in phase.
In this application, it includes the following basic blocks.
. The Voltage-Controlled Oscillator to generate the output frequency
. The divider P to devide the reference frequency by p
. The divider M to devide the VCO output frequency by m
. The divider S to divide
the VCO output frequency by s
. The phase&frequency detector detects the phase difference between the reference frequency
and the output frequency (after division) and control the charge pump voltage.
. The loop filter to filter out
high frequency components in charge pump voltage and give
smooth and clean control to VCO
The m, p, s values can be programmed by
16bit
digital
data from the external
the PLL can be locked onto the desired frequency.
source.
So,
Fout = ( m * Fin ) / ( p*s )
Fin = 14.318MHz, m=M+8 , p=P+2, s=2^S
Digital data format:
NOTES
. S1 - S0 : Output Frequency Scaler
. M7 - M0 : VCO Frequency Divider
. P5 - P0 : Reference Frequency Input Divider
Main Divider
Pre Divider
Post Scaler
M7,M6,M5,M4,M3,M2,M1,M0
P5,P4,P3,P2,P1,P0
S0,S1
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