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參數(shù)資料
| 型號(hào)： | ALD500ASWCL |
| 廠商： | Advanced Linear Devices Inc |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 17BIT DUAL 16WSOIC |
| 標(biāo)準(zhǔn)包裝： | 46 |
| 位數(shù)： | 17 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | * |
8
Advanced Linear Devices
ALD500AU/ALD500A/ALD500
Differential Inputs (V+IN,V-IN)
The ALD500AU/ALD500A/ALD500 operates with differential
voltages within the input amplifier common-mode voltage
range. The amplifier common-mode range extends from 1.5V
below positive supply to 1.5V above negative supply. Within
this common-mode voltage range, common-mode rejection is
typically 95dB.
The integrator output also follows the common-mode voltage.
When large common-mode voltages with near full-scale
differential input voltages are applied, the input signal drives
the integrator output to near the supply rails where the
integrator output is near saturation. Under such conditions,
linearity of the converter may be adversely affected as the
integrator swing can be reduced. The integrator output must
not be allowed to saturate. Typically, the integrator output can
swing to within 0.9V of either supply rails without loss of
linearity.
Analog Ground
Analog Ground is V-IN during Auto Zero Phase and Reference
Voltage Deintegration Phase. If V-IN is different from analog
ground, a common-mode voltage exists at the inputs. This
common mode signal is rejected by the high common mode
rejection ratio of the converter. In most applications, V-IN is
set at a fixed known voltage (i.e., power supply ground). All
other ground connections should be connected to digital
ground in order to minimize noise at the inputs.
Differential Reference (V+REF, V-REF)
The reference voltage can be anywhere from 1V of the power
supply voltage rails of the converter. Roll-over error is caused
by the reference capacitor losing or gaining charge due to the
stray capacitance on its nodes. The difference in reference for
(+) or (-) input voltages will cause a roll-over error. This error
can be minimized by using a large reference capacitor in
comparison to the stray capacitance.
Phase Control Inputs (A, B)
The A and B logic inputs select the ALD500AU/ALD500A/
ALD500 operating phase. The A and B inputs are normally
driven by a microprocessor I/O port or external logic, using
CMOS logic levels. For logic control functions of A and B logic
inputs, see Table 1.
Comparator Output (COUT)
By monitoring the comparator output during the Input Signal
Integration Phase, which is a fixed signal integrate time
period, the input signal polarity can be determined by the
microcontroller controlling the conversion. The comparator
output is HIGH for positive signals and LOW for negative
signals during the Input Signal Integration Phase. The state of
the comparator should be checked by the microcontroller at
the end of the Input Signal Integration Phase, just before
transition to the Reference Voltage Deintegration Phase. For
very low level input signals noise may cause the comparator
output state to toggle between positive and negative states.
For the ALD500AU/ALD500A/ALD500, this noise has been
minimized to typically within one count.
At the start of the Reference Voltage Deintegration Phase,
comparator output is set to HIGH state. During the Reference
Voltage Deintegration Phase, the microcontroller must monitor
the comparator output to make a HIGH-to-LOW transition as
the integrator output ramp crosses zero relative to analog
ground.
This transition indicates that the conversion is
complete. The microcontroller then stops and records the
pulse count. The internal comparator delay is 1
sec, typically.
The comparator output is undefined during the Auto Zero
Phase.
Figure 4. Comparator Output
ANALOG INPUT
INTEGRATE
REFERENCE
DEINTEGRATE
ZERO
CROSSING
COMPARATOR
OUTPUT
(COUT)
REFERENCE
DEINTEGRATE
ZERO
CROSSING
INTEGRATOR
OUTPUT
(VINT)
ANALOG INPUT
INTEGRATE
INTEGRATOR
OUTPUT
(VINT)
Negative Input Signal (VIN)
Positive Input Signal (VIN)
EXTERNAL INPUT
POLARITY DETECTION
COMPARATOR
OUTPUT
(COUT)
0V
EXTERNAL INPUT
POLARITY DETECTION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ALD500AU | 制造商:ALD 制造商全稱:Advanced Linear Devices 功能描述:PRECISION INTEGRATING ANALOG PROCESSOR |
| ALD500AUPC | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18 Bit A/D Processor RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ALD500AUPCL | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18 Bit A/D Processor RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ALD500AUSC | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18 Bit A/D Processor RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ALD500AUSCL | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18 Bit A/D Processor RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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