TA = 25" />
參數(shù)資料
型號： ALD500ASWCL
廠商： Advanced Linear Devices Inc
文件頁數(shù)： 7/11頁
文件大?。?/td> 0K
描述： IC ADC 17BIT DUAL 16WSOIC
標(biāo)準(zhǔn)包裝： 46
位數(shù)： 17
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 10mW
電壓電源： 雙 ±
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 管件
輸入數(shù)目和類型： *
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
5
DC ELECTRICAL CHARACTERISTICS
TA = 25°C V+ = +5.0V V- = -5.0V (VSUPPLY = ±5.0 V) unless otherwise specified; CAZ = CREF = 0.47f
500AU
500A
500
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions
Supply Current
IS
0.6
1.0
0.6
1.0
0.6
1.0
mA
V
+ = 5V , A =1,B=1
Power Dissipation
PD
10
mW
VSUPPLY = ±5V
Positive Supply Range
V+S
4.5
5.5
4.5
5.5
4.5
5.5
V
Note 4
Negative Supply Range
V-S
-4.5
-5.5
-4.5
-5.5
-4.5
-5.5
V
Note 4
Comparator Logic 1,
VOH
44
4
V
ISOURCE = 400A
Output High
Comparator Logic 0,
VOL
0.4
V
ISINK = 1.1mA
Output Low
Logic 1, Input High
VIH
3.5
V
Voltage
Logic 0, Input Low
VIL
11
1
V
Voltage
Logic Input Current
IL
0.01
A
Comparator Delay
tD
11
1
sec
Note 5
NOTES:
1. Integrate time
≥ 66 msec., Auto Zero time ≥ 66 msec., VINT = 4V, VIN = 2.0V Full Scale
Resolution = VINT /integrate time/clock period
2. End point linearity at
±1/4, ±1/2, ±3/4 Full Scale after Full Scale adjustment.
3. Rollover Error also depends on CINT, CREF, CAZ characteristics.
4. Contact factory for other power supply operating voltage ranges, including Vsupply =
±3V or Vsupply = ±2.5V.
5. Recommended selection of clock periods of one of the following:
t clk = 0.27
sec, 0.54sec, or 1.09sec
which corresponds to clock frequencies of 3.6864 MHz, 1.8432 MHz, 0.9216 MHz respectively.
~
Figure 3. ALD500 TIMING DIAGRAM
~ ~
66.667 msec.
123,093
Clock Pulses
Positive Input Signal
Negative Input Signal
~ ~
66.667 msec.
0.5416
s
123,093
Clock Pulses
~ ~
COUT
B INPUT
A INPUT
1.8432 MHz Clock
1 Conversion Cycle
Auto Zero
Phase
Input Signal
Integration
Phase
Reference
Voltage
Deintegration
Phase
Integrator Zero
Phase
Auto Zero
Phase
Fixed number
of clock pulses
by design.
Variable
number of
clock pulses.
~
Clock data in
or clock data out
of counters within the
the microcontroller
or fixed logic controller,
as needed.
Fixed period of
approx.1 msec.
At VIN MAX,
max. number of
clock pulses
= 246,185
NOT VALID
Stop counter upon
detection of comparator
output going from high
to low state.
START DEINTEGRATION CYCLE
START INTEGRATION CYCLE
START
CONVERSION
CYCLE
~ ~
START INTEGRATOR ZERO CYCLE
COUT
NOT VALID
REPEAT
CONVERSION
CYCLE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ALD500AU 制造商:ALD 制造商全稱:Advanced Linear Devices 功能描述:PRECISION INTEGRATING ANALOG PROCESSOR
ALD500AUPC 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18 Bit A/D Processor RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ALD500AUPCL 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18 Bit A/D Processor RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ALD500AUSC 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18 Bit A/D Processor RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ALD500AUSCL 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18 Bit A/D Processor RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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