參數(shù)資料
型號(hào): AM1808BZCEA3
廠商: Texas Instruments
文件頁(yè)數(shù): 225/264頁(yè)
文件大?。?/td> 0K
描述: IC ARM9 CORTEX MCU 361NFBGA
標(biāo)準(zhǔn)包裝: 160
系列: ARM9
處理器類型: ARM 微處理器
速度: 375MHz
電壓: 1.14 V ~ 1.32 V
安裝類型: 表面貼裝
封裝/外殼: 361-LFBGA
供應(yīng)商設(shè)備封裝: 361-NFBGA(13x13)
包裝: 托盤
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SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
4.3
Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly
recommended
that
an
external
pullup/pulldown
resistor
be
implemented.
Although,
internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value,
providing external connectivity can help ensure that valid logic levels are latched on these device boot and
configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration
pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the IO supply rail.
For most systems, a 1-k
resistor can be used to oppose the IPU/IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
For most systems, a 20-k
resistor can be used to compliment the IPU/IPD on the boot and
configuration pins while meeting the above criteria. Users should confirm this resistor value is correct
for their specific application.
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH)
for the device, see Section 5.3, Recommended Operating Conditions.
For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
Copyright 2010–2014, Texas Instruments Incorporated
Device Configuration
63
Product Folder Links: AM1808
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