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參數(shù)資料
| 型號： | AM28F512A-70JCB |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Quadruple 2-Input Positive-Nor Gates 14-SOIC -40 to 85 |
| 中文描述： | 四2正輸入或非門 14-SOIC封裝；-40℃到85℃ |
| 文件頁數(shù)： | 32/34頁 |
| 文件大?。?/td> | 463K |
| 代理商： | AM28F512A-70JCB |
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Am28F512A
7
PIN DESCRIPTION
A0–A15
Address Inputs for memory locations. Internal latches
hold addresses during write cycles.
CE# (E#)
Chip Enable active low input activates the chip’s con-
trol logic and input buffers. Chip Enable high will dese-
lect the device and operates the chip in stand-by mode.
DQ0–DQ7
Data Inputs during memory write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.
NC
No Connect-corresponding pin is not connected
internally to the die.
OE# (G#)
Output Enable active low input gates the outputs of the
device through the data buffers during memory read
cycles. Output Enable is high during command
sequencing and program/erase operations.
VCC
Power supply for device operation. (5.0 V
± 5% or 10%)
VPP
Program voltage input. VPP must be at high voltage in
order to write to the command register. The command
register controls all functions required to alter the mem-
ory array contents. Memory contents cannot be altered
when VPP ≤ VCC +2 V.
VSS
Ground.
WE# (W#)
Write Enable active low input controls the write function
of the command register to the memory array. The tar-
get address is latched on the falling edge of the Write
Enable pulse and the appropriate data is latched on the
rising edge of the pulse. Write Enable high inhibits
writing to the device.
相關PDF資料 |
PDF描述 |
|---|---|
| AM28F512A-70JE | Quadruple 2-Input Positive-Nor Gates 14-SOIC -40 to 85 |
| AM28F512A-70JEB | Quadruple 2-Input Positive-Nor Gates 14-SOIC -40 to 85 |
| AM28F512A-70JI | Quadruple 2-Input Positive-Nor Gates 14-SO -40 to 85 |
| AM28F512A-70JIB | Quadruple 2-Input Positive-Nor Gates 14-SO -40 to 85 |
| AM28F512A-70PC | 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms |
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