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參數(shù)資料
| 型號： | AM29BDD160GB54DPBI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 512K X 32 FLASH 2.7V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, BGA-80 |
| 文件頁數(shù)： | 50/80頁 |
| 文件大?。?/td> | 3476K |
| 代理商： | AM29BDD160GB54DPBI |
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52
Am29BDD160G
Note:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. 2.DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, two immediately consecutive read cycles to
any address cause DQ6 to toggle. When the opera-
tion is co m p lete , DQ6 s tops to ggling. Fo r
asynchronous mode, either OE# or CE# can be used
to control the read cycles. For synchronous mode,
the rising edge of ADV# is used or the rising edge of
clock while ADV# is Low.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 s, then returns to
reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sec-
tors that are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sec-
tors are erasing or erase-suspended. Alternatively,
the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 s after the pro-
gram command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 23 shows the outputs for Toggle Bit I on DQ6.
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section Reading Toggle Bits DQ6/DQ2
explains the algorithm. Figure 25 in the AC Charac-
teristics section shows the toggle bit timing
diagrams. Figure 25 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II. Figure 27 shows the
timing diagram for synchronous toggle bit status.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, in-
dicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in
progress), or whether that sector is erase-sus-
pended. Toggle Bit II is valid after the rising edge of
the final WE# pulse in the command sequence.
DQ2 toggles when the system performs two immedi-
ately consecutive reads at addresses within those
sectors that have been selected for erasure. (For
asynchronous mode, either OE# or CE# can be used
to control the read cycles. For synchronous mode,
ADV# is used.) But DQ2 cannot distinguish whether
the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and
mode information. Refer to Table 23 to compare out-
puts for DQ2 and DQ6.
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