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參數(shù)資料
| 型號： | AM29BDD160GB64CKE |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 512K X 32 FLASH 2.7V PROM, 64 ns, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 32/80頁 |
| 文件大?。?/td> | 3476K |
| 代理商： | AM29BDD160GB64CKE |
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Am29BDD160G
Unlock Bypass Chip Erase Command
The Unlock Bypass Chip Erase command is a 2-cycle
command that consists of the erase setup command
(80h) and the actual chip erase command (10h).
This command does not require the two-cycle “un-
lock” sequence since the Unlock Bypass command
was previously issued. Unlike the standard erase
command, there is no Unlock Bypass Erase Suspend
or Erase Resume commands.
To return back to standard read operations, the Un-
lock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if
the SecSi sector is enabled.
Unlock Bypass CFI Command
The Unlock Bypass CFI command is available for
PROM programmers and target systems to read the
CFI codes while in Unlock Bypass mode. See Com-
mon Flash Memory Interface (CFI) for specific CFI
codes.
To return back to standard read operations, the Un-
lock Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if
the SecSi sector is enabled.
The Unlock Bypass Reset command places the device
in standard read/reset operating mode. Once exe-
cuted, normal read operations and user command
sequences are available for execution.
The Unlock Bypass Program Command is ignored if
the SecSi sector is enabled.
Chip Erase Command
The Chip Erase command is used to erase the entire
flash memory contents of the chip by issuing a single
command. Chip erase is a six-bus cycle operation.
There are two “unlock” write cycles, followed by writ-
ing the erase “set up” command. Two more “unlock”
write cycles are followed by the chip erase com-
mand. Chip erase does not erase protected sectors.
The chip erase operation initiates the Embedded
Erase algorithm, which automatically preprograms
and verifies the entire memory to an all zero pattern
prior to electrical erase. The system is not required
to provide any controls or timings during these oper-
ations. Note that a hardware reset immediately
terminates the programming operation. The com-
mand sequence should be reinitiated once that bank
has returned to reading array data, to ensure data
integrity.
The Embedded Erase algorithm erase begins on the
rising edge of the last WE# or CE# pulse (whichever
occurs first) in the command sequence. The status of
the erase operation is determined three ways:
■
Data# polling of the DQ7 pin (see DQ7: Data#
Polling)
■
Checking the status of the toggle bit DQ6 (see
DQ6: Toggle Bit I)
■
Checking the status of the RY/BY# pin (see RY/
BY#: Ready/Busy#)
Once erasure has begun, only the Erase Suspend
command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete,
the device returns to reading array data, and ad-
dresses are no longer latched. Note that an address
change is required to begin read valid array data.
Figure 5 illustrates the Embedded Erase Algorithm.
See the Erase/Program Operations tables in AC
Characteristics for parameters, and to Figure 22 for
timing diagrams.
Sector Erase Command
The Sector Erase command is used to erase individ-
ual sectors or the entire flash memory contents.
Sector erase is a six-bus cycle operation. There are
two “unlock” write cycles, followed by writing the
erase “set up” command. Two more “unlock” write
cycles are then followed by the erase command
(30h). The sector address (any address location
within the desired sector) is latched on the falling
edge of WE# or CE# (whichever occurs last) while
the command (30h) is latched on the rising edge of
WE# or CE# (whichever occurs first).
Specifying multiple sectors for erase is accomplished
by writing the six bus cycle operation, as described
above, and then following it by additional writes of
only the last cycle of the Sector Erase command to
addresses or other sectors to be erased. The time
between Sector Erase command writes must be less
than 80 s, otherwise the command is rejected. It is
recommended that processor interrupts be disabled
during this time to guarantee this critical timing con-
dition. The interrupts can be re-enabled after the last
Sector Erase command is written. A time-out of 80
s from the rising edge of the last WE# (or CE#) will
initiate the execution of the Sector Erase com-
mand(s). If another falling edge of the WE# (or
CE#) occurs within the 80 s time-out window, the
timer is reset. Once the 80 s window has timed out
and erasure has begun, only the Erase Suspend
command is recognized (see Sector Erase and Pro-
gram Suspend Command and Sector Erase and
Program Resume Command sections). If that occurs,
the sector erase command sequence should be reini-
tiated once that bank has returned to reading array
data, to ensure data integrity. Loading the sector
erase registers may be done in any sequence and
with any number of sectors.
Sector erase does not require the user to program
the device prior to erase. The device automatically
preprograms all memory locations, within sectors to
be erased, prior to electrical erase. When erasing a
sector or sectors, the remaining unselected sectors
or the write protected sectors are unaffected. The
system is not required to provide any controls or
timings during sector erase operations. The Erase
Suspend and Erase Resume commands may be writ-
ten as often as required during a sector erase
operation.
相關(guān)PDF資料 |
PDF描述 |
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| AM29BDD160GB64CKF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB64CKI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB64CKK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB65APBE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB65APBI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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