20
Am29BL802C
22371C7 November 3, 2006
D A T A S H E E T
Command Definitions
Table 4.
Am29BL802C Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the
autoselect command sequence, all bus cycles are write
cycles.
4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles.
5. Address bits A18–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array
data.
7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a
read cycle.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
10. The data is 00h if the device is in asynchronous mode and
01h if in synchronous (burst) mode.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass
mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
14. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
C
Bus Cycles (Notes 2–5)
Third
Addr
Data
First
Second
Addr
Fourth
Addr
Fifth
Sixth
Addr
RA
XXX
555
555
Data
RD
F0
AA
AA
Data
Data
Addr Data
Addr
Data
Read (Note 6)
Reset (Note 7)
Manufacturer ID
Device ID, Bottom Boot Block
1
1
4
4
A
(
2AA
2AA
55
55
555
555
90
90
X00
X01
(SA)
X02
01
2281
0000
0001
0000
0001
PD
Sector Protect Verify (Note 9)
4
555
AA
2AA
55
555
90
Burst Mode Status (Note 10)
4
555
AA
2AA
55
555
90
X03
Program
Unlock Bypass
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
Chip Erase
Sector Erase
Erase Suspend (Note 13)
Erase Resume (Note 14)
Burst Mode
Burst Mode Enable
Burst Mode Disable
4
3
2
2
6
6
1
1
555
555
XXX
XXX
555
555
XXX
XXX
AA
AA
A0
90
AA
AA
B0
30
2AA
2AA
PA
XXX
2AA
2AA
55
55
PD
00
55
55
555
555
A0
20
PA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
4
4
555
555
AA
AA
2AA
2AA
55
55
555
555
C0
C0
XXX
XXX
01
00