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參數(shù)資料
| 型號(hào)： | AM29DL640H70WHI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
| 中文描述： | 4M X 16 FLASH 3V PROM, 70 ns, PBGA63 |
| 封裝： | 12 X 11 MM, 0.80 MM PITCH, FBGA-63 |
| 文件頁(yè)數(shù)： | 38/54頁(yè) |
| 文件大小： | 880K |
| 代理商： | AM29DL640H70WHI |
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36
Am29DL640H
February 9, 2005
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 14 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V
CC
/2. The time from OE# high to
the data bus driven to V
CC
/2 is taken as t
DF
.
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
55
60
70
90
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
55
60
70
90
ns
t
AVQV
t
ACC
Address to Output Delay
CE#,
OE# = V
IL
Max
55
60
70
90
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
55
60
70
90
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
25
30
35
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Notes 1, 3)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 3)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
5
10
ns
t
OH
t
CE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
Figure 14.
Read Operation Timings
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| AM29DL640H70WHIN | 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
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| AM29DL640H90WHE | 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
| AM29DL640H60WHEN | 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
| AM29DL640H60WHI | 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory |
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