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參數(shù)資料
| 型號(hào)： | AM29F040B-90PK |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| 中文描述： | 512K X 8 FLASH 5V PROM, 90 ns, PDIP32 |
| 封裝： | LEAD FREE, PLASTIC, MO-015AP, DIP-32 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 534K |
| 代理商： | AM29F040B-90PK |
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November 1, 2006 21445E5
Am29F040B
7
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The register is composed of latches that store
the commands, along with the address and data infor-
mation needed to execute the command. The contents
of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F040B Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Note:
See the “Sector Protection/Unprotection” section. for more information.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See
“Reading Array Data”
for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
CC1
in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the
“Command Defini-
tions”
section for details on erasing a sector or the
entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the
“Autoselect Mode”
and
“Autoselect
Command Sequence”
sections for more information.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to
“Write Operation
Status”
for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
Operation
CE#
OE#
WE#
A0–A20
DQ0–DQ7
Read
L
L
H
A
IN
D
OUT
Write
L
H
L
A
IN
D
IN
CMOS Standby
V
CC
± 0.5 V
X
X
X
High-Z
TTL Standby
H
X
X
X
High-Z
Output Disable
L
H
H
X
High-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29F040 | 4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| AM29F040B-1 | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| AM29F040-55JEB | 4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| AM29F040-150EIB | 4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| AM29F040-120EEB | 4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F080B-120EC | 制造商:Advanced Micro Devices 功能描述: |
| AM29F080B-120EF | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 8Mbit 1M x 8bit 120ns 40-Pin TSOP |
| AM29F080B-120SC | 制造商:Spansion 功能描述:IC,EEPROM,NOR FLASH,1MX8,CMOS,SOP,44PIN,PLASTIC |
| AM29F080B-120SC/T | 制造商:Spansion 功能描述:FLASH PARALLEL 5V 8MBIT 1MX8 120NS 44SOIC - Rail/Tube |
| AM29F080B-55EF | 功能描述:閃存 8M (1MX8) 55ns 5v Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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