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參數(shù)資料
| 型號： | AM29LL800BT-200EI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
| 中文描述： | 1M X 8 FLASH 2.2V PROM, 200 ns, PDSO48 |
| 封裝： | TSOP-48 |
| 文件頁數(shù)： | 14/40頁 |
| 文件大?。?/td> | 534K |
| 代理商： | AM29LL800BT-200EI |
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14
Am29LL800B
A D V A N C E I N F O R M A T I O N
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code. A
read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) re-
turns 01h if that sector is protected, or 00h if it is unpro-
tected. Refer to Tables 2 and 3 for valid sector
addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
5 shows the address and data requirements for the
byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset
immediately terminates the program-
ming operation. The Byte Program command se-
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from a “0” back to a “1”.
Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock by-
pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de-
vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 5 shows the requirements for the com-
mand sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. The device then re-
turns to reading array data.
Figure 4 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
相關PDF資料 |
PDF描述 |
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| Am29LL800BT-200EIB | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
| AM29LL800BT-200FC | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
| Am29LL800BT-200FCB | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
| AM29LL800BT-200FI | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
| Am29LL800BT-200FIB | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
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