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參數(shù)資料
| 型號： | AM29LV001BT-5JC |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 1兆位（128畝× 8位）的CMOS 3.0伏，只引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 20/43頁 |
| 文件大?。?/td> | 493K |
| 代理商： | AM29LV001BT-5JC |
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18
Am29LV001B
21557F4 May 5, 2006
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7.
Table 6 on page 21
and the following subsections
describe the functions of these bits. DQ7, and DQ6
each offer a method for determining whether a program
or erase operation is complete or in progress. These
three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 μs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 μs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the
following
read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low.
Figure 17, on
page 31
, Data# Polling Timings (During Embedded
Algorithms), illustrates this.
Table 6 on page 21
shows the outputs for Data# Polling
on DQ7.
Figure 5
shows the Data# Polling algorithm.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
DQ7 = Data
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5.
Data# Polling Algorithm
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