參數(shù)資料
型號： AM29LV008BB120FE
英文描述： Slave Motion SPI/Host Register Interface Accelerator Verilog Module
中文描述： x8閃存EEPROM的
文件頁數(shù)： 24/35頁
文件大?。?/td> 744K
代理商： AM29LV008BB120FE
24
Am29LV040B
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 6 for test specifications.
Parameter
Description
Speed Option
JEDEC
Std
Test Setup
-60R
-70
-90
-120
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
60
70
90
120
ns
t
AVQV
t
ACC
Address to Output Delay
CE# = V
IL
OE# = V
IL
Max
60
70
90
120
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
60
70
90
120
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
30
35
50
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1)
Max
25
25
30
30
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Note 1)
Max
25
25
30
30
ns
t
OEH
Output Enable
Hold Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
Min
0
ns
t
CE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
ACC
t
RC
t
OEH
t
OE
0 V
t
DF
t
OH
Figure 11.
Read Operations Timings
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