參數(shù)資料
型號: AM29LV320DB90EI
廠商: ADVANCED MICRO DEVICES INC
元件分類: PROM
英文描述: 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory
中文描述: 2M X 16 FLASH 3V PROM, 90 ns, PDSO48
封裝: MO-142B, TSOP-48
文件頁數(shù): 32/57頁
文件大?。?/td> 636K
代理商: AM29LV320DB90EI
30
Am29LV320D
December 14, 2005
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 15 on page 33 and the following
subsections describe the function of these bits. DQ7
and DQ6 each offer a method for determining whether
a program or erase operation is complete or in
progress. The device also provides a hardware-based
output signal, RY/BY#, to determine whether an Em-
bedded Program or Erase operation is in progress or
is completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Program or Erase algo-
rithm is in progress or completed, or whether a device
is in Erase Suspend. Data# Polling is valid after the
rising edge of the final WE# pulse in the command se-
quence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 μs, then the device returns to the read
mode.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 μs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device completes
the program or erase operation and DQ7 contains
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 appears on succes-
sive read cycles.
Table 15 on page 33 shows the outputs for Data# Poll-
ing on DQ7.
Figure 6, on page 30
shows the Data#
Polling algorithm.
Figure 20, on page 44
in the
AC
Characteristics
section shows the Data# Polling timing
diagram.
Figure 6.
Data# Polling Algorithm
DQ7 = Data
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
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