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參數(shù)資料
| 型號(hào)： | AM29LV652DU12RMAE |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO Control |
| 中文描述： | 16M X 8 FLASH 3V PROM, 120 ns, PBGA63 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-63 |
| 文件頁數(shù)： | 25/55頁 |
| 文件大?。?/td> | 1181K |
| 代理商： | AM29LV652DU12RMAE |
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October 29, 2004
Am29LV652D
23
P R E L I M I N A R Y
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to
Table 10, on
page 30
for command definitions). In addition, the fol-
lowing hardware data protection measures prevent ac-
cidental erasure or programming, which might
otherwise be caused by spurious system level signals
during V
CC
power-up and power-down transitions, or
from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until V
CC
is greater than V
LKO
. The
system must provide the proper signals to the control
inputs to prevent unintentional writes when V
CC
is
greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#,
CE2#, or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
, CE2# = V
IH
or WE# = V
IH
. To initiate a
write cycle, CE# (or CE2#), and WE# must be a logical
zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = CE2# = V
IL
and OE# = V
IH
during
power up, the device does not accept commands on
the rising edge of WE#. The internal state machine is
automatically reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
The Am29LV652 is a two die solution which appears
as two 64 Mbit Am29LV065 devices in the system.
This allows the same CFI information to be used be-
cause the system “sees” two 64 Mbit devices, not a
single 128 Mbit device.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, any time the
device is ready to read array data (addresses are don’t
care). The system can read CFI information at the ad-
dresses given in
Table 6, on page 23
to
Table 9, on
page 25
. To terminate reading CFI data, the system
must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in
Table 6, on
page 23
to
Table 9, on page 25
. The system must
write the reset command to return the device to the
autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
Table 6.
CFI Query Identification String
Addresses (x8)
Data
Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
00h
00h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
00h
00h
Address for Alternate OEM Extended Table (00h = none exists)
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