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    參數(shù)資料
    型號(hào): AM29LV652DU12RMAI
    廠商: SPANSION LLC
    元件分類(lèi): DRAM
    英文描述: 128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO Control
    中文描述: 16M X 8 FLASH 3V PROM, 120 ns, PBGA63
    封裝: 11 X 12 MM, 0.80 MM PITCH, FBGA-63
    文件頁(yè)數(shù): 29/55頁(yè)
    文件大?。?/td> 1181K
    代理商: AM29LV652DU12RMAI
    October 29, 2004
    Am29LV652D
    27
    P R E L I M I N A R Y
    two unlock cycles. This is followed by a third write
    cycle containing the unlock bypass command, 20h.
    The device then enters the unlock bypass mode. A
    two-cycle unlock bypass program command sequence
    is all that is required to program in this mode. The first
    cycle in this sequence contains the unlock bypass pro-
    gram command, A0h; the second cycle contains the
    program address and data. Additional data is pro-
    grammed in the same manner. This mode dispenses
    with the initial two unlock cycles required in the stan-
    dard program command sequence, resulting in faster
    total programming time.
    Table 10, on page 30
    shows
    the requirements for the command sequence.
    During the unlock bypass mode, only the Unlock By-
    pass Program and Unlock Bypass Reset commands
    are valid. To exit the unlock bypass mode, the system
    must issue the two-cycle unlock bypass reset com-
    mand sequence. The first cycle must contain the data
    90h. The second cycle must contain the data 00h. The
    device then returns to the read mode.
    The device offers accelerated program operations
    through ACC. When the system asserts V
    HH
    on ACC,
    the device automatically enters the Unlock Bypass
    mode. The system may then write the two-cycle Un-
    lock Bypass program command sequence. The device
    uses the higher voltage on ACC to accelerate the op-
    eration.
    Note that ACC must not be at V
    HH
    for opera-
    tions other than accelerated programming, or device
    damage may result.
    Figure 3, on page 27
    illustrates the algorithm for the
    program operation. Refer to the
    “Erase and Program
    Operations” on page 41
    table in the AC Characteris-
    tics section for parameters, and
    Figure 15, on page 42
    for timing diagrams.
    Figure 3.
    Program Operation
    Chip Erase Command Sequence
    Chip erase is a six bus cycle operation. The chip erase
    command sequence is initiated by writing two unlock
    cycles, followed by a set-up command. Two additional
    unlock write cycles are then followed by the chip erase
    command, which in turn invokes the Embedded Erase
    algorithm. The device does
    not
    require the system to
    preprogram prior to erase. The Embedded Erase algo-
    rithm automatically preprograms and verifies the entire
    memory for an all zero data pattern prior to electrical
    erase. The system is not required to provide any con-
    trols or timings during these operations.
    Table 10, on
    page 30
    shows the address and data requirements for
    the chip erase command sequence.
    START
    Write Program
    Command Sequence
    Data Poll
    from System
    Verify Data
    No
    Yes
    Last Address
    No
    Yes
    Programming
    Completed
    Increment Address
    Embedded
    Program
    algorithm
    in progress
    Note:
    See
    Table 10, on page 30
    for program command
    sequence.
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