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參數(shù)資料
| 型號(hào)： | AM29LV652DU12RMAK |
| 廠商： | SPANSION LLC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO Control |
| 中文描述： | 16M X 8 FLASH 3V PROM, 120 ns, PBGA63 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-63 |
| 文件頁(yè)數(shù)： | 41/55頁(yè) |
| 文件大小： | 1181K |
| 代理商： | AM29LV652DU12RMAK |
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October 29, 2004
Am29LV652D
39
P R E L I M I N A R Y
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. All test setups assume V
IO
= V
CC
.
2. Not 100% tested.
3. See
Figure 11, on page 38
and
Table 12, on page 38
for
test specifications
4. CE# can be replaced with CE2# when referring to the second device within the package.
.
Parameter
Description
Test Setup
(Note 1)
Speed Options
JEDEC
Std.
90R
12R
Unit
t
AVAV
t
RC
Read Cycle Time (Note 2)
Min
90
120
ns
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
90
120
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
90
120
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
35
50
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 2)
Max
30
30
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Note 2)
Max
30
30
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold
Time (Note 2)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
OH
t
CE
Outputs
WE#
Addresses
CE# or CE2#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
ACC
t
RC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
Figure 13.
Read Operation Timings
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