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參數資料
| 型號： | AM29LV652DU90RMAI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | Varistor; Package/Case:0805; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:14V; Output Current Max:0.75A; Output Voltage Max:32V |
| 中文描述： | 16M X 8 FLASH 3V PROM, 90 ns, PBGA63 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-63 |
| 文件頁數： | 26/55頁 |
| 文件大?。?/td> | 1181K |
| 代理商： | AM29LV652DU90RMAI |
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24
Am29LV652D
October 29, 2004
P R E L I M I N A R Y
Table 7.
System Interface String
Table 8.
Device Geometry Definition
Addresses (x8)
Data
Description
1Bh
27h
V
CC
Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
36h
V
CC
Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
00h
V
PP
Min. voltage (00h = no V
PP
input present)
1Eh
00h
V
PP
Max. voltage (00h = no V
PP
input present)
1Fh
04h
Typical timeout per single byte write 2
N
μs
20h
00h
Typical timeout for Min. size buffer write 2
N
μ
s (00h = not supported)
21h
0Ah
Typical timeout per individual block erase 2
N
ms
22h
00h
Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h
05h
Max. timeout for byte write 2
N
times typical
24h
00h
Max. timeout for buffer write 2
N
times typical
25h
04h
Max. timeout per individual block erase 2
N
times typical
26h
00h
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
Addresses (x8)
Data
Description
27h
17h
Device Size = 2
N
byte
28h
29h
00h
00h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
00h
00h
Max. number of bytes in multi-byte write = 2
N
(00h = not supported)
2Ch
01h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
7Fh
00h
00h
01h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
00h
00h
00h
00h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
00h
00h
00h
00h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
00h
00h
00h
00h
Erase Block Region 4 Information (refer to CFI publication 100)
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