參數(shù)資料
型號(hào)： AM29LV800DT-90WCI
廠商： ADVANCED MICRO DEVICES INC
元件分類： PROM
英文描述： 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
中文描述： 512K X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： 6.15 X 8.15 MM, 0.80 MM PITCH, FBGA-48
文件頁(yè)數(shù)： 13/51頁(yè)
文件大?。?/td> 1628K
代理商： AM29LV800DT-90WCI
January 21, 2005 Am29LV800D_00_A4_E
Am29LV800D
11
P R E L I M I N A R Y
Writing Commands/Command Sequences
To write a command or command sequence
(which includes programming data to the device
and erasing sectors of memory), the system
must drive WE# and CE# to V
IL
, and OE# to
V
IH
.
For program operations, the BYTE# pin deter-
mines whether the device accepts program data
in bytes or words. Refer to “Word/Byte Configu-
ration” for more information.
The device features an
Unlock Bypass
mode to
facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write
cycles are required to program a word or byte,
instead of four. The “Word/Byte Program
Command Sequence” section has details on pro-
gramming data to the device using both stan-
dard and Unlock Bypass command sequences.
An erase operation can erase one sector, mul-
tiple sectors, or the entire device. Tables 2 and
3 indicate the address space that each sector
occupies. A “sector address” consists of the
address bits required to uniquely select a sector.
The “Command Definitions” section has details
on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect
mode. The system can then read autoselect
codes from the internal register (which is sepa-
rate from the memory array) on DQ7–DQ0.
Standard read cycle timings apply in this mode.
Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more infor-
mation.
I
CC2
in the DC Characteristics table represents
the active current specification for the write
mode. The “AC Characteristics” section contains
timing specification tables and timing diagrams
for write operations.
Program and Erase Operation Status
During an erase or program operation, the
system may check the status of the operation by
reading the status bits on DQ7–DQ0. Standard
read cycle timings and I
CC
read specifications
apply. Refer to “Write Operation Status” for
more information, and to “AC Characteristics”
for timing diagrams.
Standby Mode
When the system is not reading or writing to the
device, it can place the device in the standby
mode. In this mode, current consumption is
greatly reduced, and the outputs are placed in
the high impedance state, independent of the
OE# input.
The device enters the CMOS standby mode
when the CE# and RESET# pins are both held at
V
CC
±
0.3 V. (Note that this is a more restricted
voltage range than V
IH
.) If CE# and RESET# are
held at V
IH
, but not within V
CC
±
0.3 V, the device
will be in the standby mode, but the standby
current will be greater. The device requires stan-
dard access time (t
CE
) for read access when the
device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or pro-
gramming, the device draws active current until
the operation is completed.
In the DC Characteristics table, I
CC3
and I
CC4
represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash
device energy consumption. The device auto-
matically enables this mode when addresses
remain stable for t
ACC
+ 30 ns. The automatic
sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address
access timings provide new data when
addresses are changed. While in sleep mode,
output data is latched and always available to
the system. I
CC4
in the DC Characteristics table
represents the automatic sleep mode current
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven low for at least a
period of t
RP
, the device
immediately termi-
nates
any operation in progress, tristates all
output pins, and ignores all read/write com-
mands for the duration of the RESET# pulse.
The device also resets the internal state
machine to reading array data. The operation
that was interrupted should be reinitiated once
the device is ready to accept another command
sequence, to ensure data integrity.
Current is reduced for the duration of the
RESET# pulse. When RESET# is held at
V
SS
±0.3 V, the device draws CMOS standby
current (I
CC4
). If RESET# is held at V
IL
but not
within V
SS
±0.3 V, the standby current will be
greater.
The RESET# pin may be tied to the system reset
circuitry. A system reset would thus also reset
the Flash memory, enabling the system to read
the boot-up firmware from the Flash memory.
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