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參數(shù)資料
| 型號： | AM29SL160CB-100WCFN |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit CMOS 1.8 Volt-only Super Low Voltage Flash Memory |
| 中文描述： | 16兆位的CMOS 1.8伏只超低電壓快閃記憶體 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 1232K |
| 代理商： | AM29SL160CB-100WCFN |
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30
Am29SL160C
November 1, 2004
RY/BY#: Ready/Busy#
RY/BY# is a dedicated, open-drain output pin that indi-
cates whether an Embedded Algorithm is in progress
or complete. The RY/BY# status is valid after the rising
edge of the final WE# pulse in the command sequence.
Since RY/BY# is an open-drain output, several RY/BY#
pins can be tied together in parallel with a pull-up
resistor to V
CC
.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 13, on page 32
shows the outputs for RY/BY#.
Figure 14, on page 38
,
Figure 17, on page 41
and
Figure 18, on page 42
shows RY/BY# for reset, pro-
gram, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle (The system may use either OE#
or CE# to control the read cycles). When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6
toggles for approximately 100 μs, then returns to
reading array data. If not all selected sectors are pro-
tected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on
“DQ7: Data# Polling” on
page 29
).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 13, on page 32
shows the outputs for Toggle Bit
I on DQ6.
Figure 6, on page 31
shows the toggle bit
algorithm.
Figure 20, on page 43
shows the toggle bit
timing diagrams.
Figure 21, on page 44
shows the dif-
ferences between DQ2 and DQ6 in graphical form. See
also the subsection on
“DQ2: Toggle Bit II”
.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE# or CE# read cycle.
DQ2 toggles when the system reads at addresses
within those sectors that were selected for erasure. But
DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison,
indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are
required for sector and mode information. Refer to
Table 13, on page 32
to compare outputs for DQ2 and
DQ6.
Figure 6, on page 31
shows the toggle bit algorithm in
flowchart form, and the section “DQ2: Toggle Bit II”
explains the algorithm. See also the
“DQ6: Toggle Bit I”
subsection.
Figure 20, on page 43
shows the toggle bit
timing diagram.
Figure 21, on page 44
shows the differ-
ences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 6, on page 31
for the following discus-
sion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice
in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of
the toggle bit after the first read. After the second read,
the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the
device completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device successfully completed the
program or erase operation. If it is still toggling, the
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