參數(shù)資料
型號(hào)： AM29SL400CB100RWAI
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
中文描述： 256K X 16 FLASH 1.8V PROM, 100 ns, PBGA48
封裝： 6 X 8 MM, 0.80 MM PITCH, FBGA-48
文件頁(yè)數(shù)： 23/44頁(yè)
文件大小： 945K
代理商： AM29SL400CB100RWAI
March 3, 2005
21
A d v a n c e I n f o r m a t i o n
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time
has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a
1.
This is a
failure condition that indicates the program or erase
cycle was not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a
1
to a location that is previously
programmed to “0.”
Only an erase operation can
change a
0
back to a
1.
Under this condition, the
device halts the operation, and when the operation
has exceeded the timing limits, DQ5 produces a
1.
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
an erase operation has begun. (The sector erase
timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire
time-out also applies after each additional sector
erase command. When the time-out is complete,
DQ3 switches from
0
to
1.
If the time between addi-
tional sector erase commands from the system can
be assumed to be less than 50 μs, the system need
not monitor DQ3. See also
Sector Erase Command
Sequence on page 16
.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device
has accepted the command sequence, and then read
DQ3. If DQ3 is
1
, the internally controlled erase cycle
has begun; all further commands (other than Erase
Suspend) are ignored until the erase operation is
complete. If DQ3 is
1
, the device will accept addi-
tional sector erase commands. To ensure the com-
mand has been accepted, the system software
should check the status of DQ3 prior to and following
each subsequent sector erase command. If DQ3 is
high on the second status check, the last command
might not have been accepted.
Table 6 on page 22
shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1
No
Yes
Toggle Bit
= Toggle
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1.
Read toggle bit twice to determine whether or not it is
toggling. See text.
2.
Recheck toggle bit because it may stop toggling as DQ5
changes to
1
. See text.
Figure 6.
Toggle Bit Algorithm
(Notes
1, 2)
(Note 1)
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