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參數(shù)資料
| 型號： | AM29SL400CT120WAD |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | CAP,CERAMIC,100PF,5%,1KV |
| 中文描述： | 256K X 16 FLASH 1.8V PROM, 120 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, FBGA-48 |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 945K |
| 代理商： | AM29SL400CT120WAD |
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14
March 3, 2005
A d v a n c e I n f o r m a t i o n
Figure 2.
Temporary Sector Unprotect
Operation
Hardware Data Protection
The command sequence requirement of unlock cy-
cles for programming or erasing provides data pro-
tection against inadvertent writes (refer to
Table 5
on page 18
for command definitions). In addition,
the following hardware data protection measures
prevent accidental erasure or programming, which
might otherwise be caused by spurious system level
signals during V
CC
power-up and power-down transi-
tions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ig-
nored until V
CC
is greater than V
LKO
. The system
must provide the proper signals to the control pins to
prevent unintentional writes when V
CC
is greater
than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write
cycle, CE# and WE# must be a logical zero while
OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power
up, the device does not accept commands on the ris-
ing edge of WE#. The internal state machine is auto-
matically reset to reading array data on power-up.
Command Definitions
Writing specific address and data commands or se-
quences into the command register initiates device
operations.
Table 5 on page 18
defines the valid reg-
ister command sequences. Writing
incorrect
ad-
dress and data values
or writing them in the
improper sequence
resets the device to reading
array data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched
on the rising edge of WE# or CE#, whichever hap-
pens first. Refer to the appropriate timing diagrams
in the
AC Characteristics
section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
The system
must
issue the reset command to re-en-
able the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the
Reset
Command on page 14
section, next.
See also
Requirements for Reading Array Data on
page 9
for more information. The Read Operations
table provides the read parameters, and
Figure 14
on page 28
shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading
array data. Once erasure begins, however, the de-
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = V
ID
(Note 1)
Notes:
1.
All protected sectors unprotected.
2.
All previously protected sectors are protected once
again.
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