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| 型號： | AM29SL400CT150WAI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory |
| 中文描述： | 256K X 16 FLASH 1.8V PROM, 150 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 0.80 MM PITCH, FBGA-48 |
| 文件頁數(shù)： | 22/44頁 |
| 文件大小： | 945K |
| 代理商： | AM29SL400CT150WAI |
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20
March 3, 2005
A d v a n c e I n f o r m a t i o n
ming in the Erase Suspend mode.) If the output is
high (Ready), the device is ready to read array data
(including during the Erase Suspend mode), or is in
the standby mode.
Table 6 on page 22
shows the outputs for RY/BY#.
Figure 14 on page 28
,
Figure 17 on page 31
, and
Figure 18 on page 32
shows RY/BY# for reset, pro-
gram, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle (The system may use either OE# or
CE# to control the read cycles). When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 μs, then returns to read-
ing array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sec-
tors that are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively eras-
ing (that is, the Embedded Erase algorithm is in
progress), DQ6 toggles. When the device enters the
Erase Suspend mode, DQ6 stops toggling. However,
the system must also use DQ2 to determine which
sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection
on
DQ7: Data# Polling on page 19
).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the pro-
gram command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 6 on page 22
shows the outputs for Toggle Bit I
on DQ6.
Figure 6 on page 21
shows the toggle bit
algorithm.
Figure 20 on page 33
shows the toggle
bit timing diagrams. Figure 21 shows the differences
between DQ2 and DQ6 in graphical form. See also
the subsection on
DQ2: Toggle Bit II on page 20
.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, in-
dicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in
progress), or whether that sector is erase-sus-
pended. Toggle Bit II is valid after the rising edge of
the final WE# pulse in the command sequence. The
device toggles DQ2 with each OE# or CE# read cy-
cle.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. But DQ2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. DQ6, by
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distin-
guish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode in-
formation. Refer to
Table 6 on page 22
to compare
outputs for DQ2 and DQ6.
Figure 6 on page 21
shows the toggle bit algorithm
in flowchart form, and the section
DQ2: Toggle Bit
II on page 20
explains the algorithm. See also the
DQ6: Toggle Bit I subsection.
Figure 20 on page 33
shows the toggle bit timing diagram.
Figure 21 on
page 34
shows the differences between DQ2 and
DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 6 on page 21
for the following dis-
cussion. Whenever the system initially begins read-
ing toggle bit status, it must read DQ7–DQ0 at least
twice in a row to determine whether a toggle bit is
toggling. Typically, the system would note and store
the value of the toggle bit after the first read. After
the second read, the system would compare the new
value of the toggle bit with the first. If the toggle bit
is not toggling, the device has completed the pro-
gram or erase operation. The system can read array
data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the sys-
tem determines that the toggle bit is still toggling,
the system also should note whether the value of
DQ5 is high (see the section on DQ5). If it is, the
system should then determine again whether the
toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle
bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is
still toggling, the device did not completed the oper-
ation successfully, and the system must write the
reset command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to
monitor the toggle bit and DQ5 through successive
read cycles, determining the status as described in
the previous paragraph. Alternatively, it may choose
to perform other system tasks. In this case, the sys-
tem must start at the beginning of the algorithm
when it returns to determine the status of the opera-
tion (top of
Figure 6 on page 21
).
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