參數(shù)資料
型號(hào)： AM41DL16X4D
英文描述： Am41DL16x4D - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述： Am41DL16x4D -堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁(yè)數(shù)： 12/63頁(yè)
文件大?。?/td> 1052K
代理商： AM41DL16X4D
Am41DL16x4D
11
P R E L I M I N A R Y
Table 1.
Device Bus Operations
—
Flash Word Mode, CIOf = V
IH
; SRAM Word Mode, CIOs = V
CC
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 8.5–12.5
V, V
HH
= 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = V
IL
, CE1#s = V
IL
and CE2s = V
IH
at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V
IL
, the boot sectors will be protected. If WP#/ACC = V
IH
the boot sectors protection will be removed.
If WP#/ACC = V
ACC
(9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “The autoselect
mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on
DQ7–DQ0. The autoselect codes can be accessed in-system through the command register. Refer to the Autoselect Command
Sequence section for more information.Sector/Sector Block Protection and Unprotection” section.
6. If WP#/ACC = V
, the two outermost boot sectors remain protected. If WP#/ACC = V
, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “The autoselect mode provides
manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. The
autoselect codes can be accessed in-system through the command register. Refer to the Autoselect Command Sequence section
for more information.Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V
HH,
all sectors will be unprotected.
Operation
(Notes 1, 2)
CE#f CE1#s CE2s OE# WE#
SA
Addr.
LB#s UB#s RESET#(Note 4)
DQ7
–
DQ0
DQ15
–
DQ8
Read from Flash
L
H
X
L
H
X
A
IN
X
X
H
L/H
D
OUT
D
OUT
X
L
Write to Flash
L
H
X
H
L
X
A
IN
X
X
H
(Note 4)
D
IN
D
IN
X
L
Standby
V
CC
±
0.3 V
H
X
X
X
X
X
X
X
V
CC
±
0.3 V
H
High-Z
High-Z
X
L
Output Disable
L
L
H
H
H
X
X
L
X
H
L/H
High-Z
High-Z
H
H
X
X
X
L
Flash Hardware
Reset
X
H
X
X
X
X
X
X
X
L
L/H
High-Z
High-Z
X
L
Sector Protect
(Note 5)
L
H
X
H
L
X
SADD,
A6 = L,
A1 = H,
A0 = L
X
X
V
ID
L/H
D
IN
X
X
L
Sector Unprotect
(Note 5)
L
H
X
H
L
X
SADD,
A6 = H,
A1 = H,
A0 = L
X
X
V
ID
(Note 6)
D
IN
X
X
L
Temporary Sector
Unprotect
X
H
X
X
X
X
X
X
X
V
ID
(Note 6)
D
IN
High-Z
X
L
Read from SRAM
H
L
H
L
H
X
A
IN
L
L
H
X
D
OUT
High-Z
D
OUT
D
OUT
High-Z
H
L
L
H
D
OUT
D
IN
High-Z
Write to SRAM
H
L
H
X
L
X
A
IN
L
L
H
X
D
IN
D
IN
H
L
L
H
D
IN
High-Z
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