參數(shù)資料
型號(hào): AM41DL32X8G
英文描述: 200NS, LCC, IND TEMP(EEPROM)
中文描述: Am41DL32x8G -堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁(yè)數(shù): 9/63頁(yè)
文件大?。?/td> 1052K
代理商: AM41DL32X8G
8
Am41DL16x4D
P R E L I M I N A R Y
PIN DESCRIPTION
A17
A0
= 18 Address Inputs (Common)
A
1, A19
A18 = 3 Address Inputs (Flash)
SA
= Highest Order Address Input
(SRAM) Byte mode
DQ15
DQ0
= 16 Data Inputs/Outputs (Common)
CE#f
= Chip Enable (Flash)
CE#s
= Chip Enable (SRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output
UB#s
= Upper Byte Control (SRAM)
LB#s
= Lower Byte Control (SRAM)
CIOf
= I/O Configuration (Flash)
CIOf = V
IH
= Word mode (x16),
CIOf = V
IL
= Byte mode (x8)
= I/O Configuration (SRAM)
CIOs = V
IH
= Word mode (x16),
CIOs = V
IL
= Byte mode (x8)
= Hardware Reset Pin, Active Low
CIOs
RESET#
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CC
s
V
SS
NC
= SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
18
16 or 8
DQ15
DQ0
A0
A17
CE#f
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
SA
A
1, A18
A19
LB#s
CIOf
CIOs
CE1#s
CE2s
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