參數(shù)資料
型號： AM41DL6408H8H70IT
廠商： Advanced Micro Devices, Inc.
英文描述： TV 6C 6#20 PIN WALL RECP
中文描述： 堆疊式多芯片封裝（MCP）閃存和SRAM
文件頁數(shù)： 5/66頁
文件大?。?/td> 1123K
代理商： AM41DL6408H8H70IT
November 24, 2003
Am41DL6408H
3
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
SRAM Word Mode, CIOs = V
CC
..................................................... 10
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
SRAM Byte Mode, CIOs = V
SS
......................................................11
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SS
;
SRAM Word Mode, CIOs = V
CC
.....................................................12
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
; SRAM
Byte Mode, CIOs = V
..................................................................13
Word/Byte Configuration ........................................................ 13
Requirements for Reading Array Data ...................................13
Writing Commands/Command Sequences ............................14
Accelerated Program Operation ..........................................14
Autoselect Functions ...........................................................14
Simultaneous Read/Write Operations with Zero Latency .......14
Standby Mode ........................................................................ 14
Automatic Sleep Mode ...........................................................15
RESET#: Hardware Reset Pin ...............................................15
Output Disable Mode ..............................................................15
Table 5. Am29DL640H Sector Architecture ....................................15
Table 6. Bank Address ....................................................................18
Table 7. SecSi
Sector Addresses ...............................................18
Sector/Sector Block Protection and Unprotection .................. 19
Table 8. Am29DL640H Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................................19
Write Protect (WP#) ................................................................19
Table 9. WP#/ACC Modes ..............................................................20
Temporary Sector Unprotect ..................................................20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21
SecSi (Secured Silicon) Sector Flash Memory Region ......22
Figure 3. SecSi Sector Protect Verify.............................................. 23
Hardware Data Protection ......................................................23
Low V
CC
Write Inhibit ...........................................................23
Write Pulse “Glitch” Protection ............................................23
Logical Inhibit ......................................................................23
Power-Up Write Inhibit .........................................................23
Common Flash Memory Interface (CFI) . . . . . . .23
Table 10. CFI Query Identification String........................................ 24
System Interface String................................................................... 24
Table 12. Device Geometry Definition ............................................ 24
Table 13. Primary Vendor-Specific Extended Query ...................... 26
Command Definitions . . . . . . . . . . . . . . . . . . . . . .27
Reading Array Data ................................................................27
Reset Command .....................................................................27
Autoselect Command Sequence ............................................27
Enter SecSi Sector/Exit SecSi Sector
Command Sequence ..............................................................27
Byte/Word Program Command Sequence .............................28
Unlock Bypass Command Sequence ..................................28
Figure 4. Program Operation .......................................................... 29
Chip Erase Command Sequence ...........................................29
Sector Erase Command Sequence ........................................29
Figure 5. Erase Operation.............................................................. 30
Erase Suspend/Erase Resume Commands ...........................30
Table 14. Am29DL640H Command Definitions.............................. 31
Write Operation Status . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data# Polling .................................................................32
Figure 6. Data# Polling Algorithm .................................................. 32
RY/BY#: Ready/Busy# ............................................................ 33
DQ6: Toggle Bit I ....................................................................33
Figure 7. Toggle Bit Algorithm........................................................ 33
DQ2: Toggle Bit II ...................................................................34
Reading Toggle Bits DQ6/DQ2 ...............................................34
DQ5: Exceeded Timing Limits ................................................34
DQ3: Sector Erase Timer .......................................................34
Table 15. Write Operation Status ................................................... 35
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36
Figure 8. Maximum Negative Overshoot Waveform...................... 36
Figure 9. Maximum Positive Overshoot Waveform........................ 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
SRAM DC and Operating Characteristics . . . . . 38
Figure 10. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents)............................................................. 39
Figure 11. Typical I
vs. Frequency............................................ 39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 12. Test Setup.................................................................... 40
Figure 13. Input Waveforms and Measurement Levels ................. 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
SRAM CE#s Timing ................................................................41
Figure 14. Timing Diagram for Alternating Between
SRAM to Flash............................................................................... 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Flash Read-Only Operations .................................................42
Figure 15. Read Operation Timings............................................... 42
Hardware Reset (RESET#) ....................................................43
Figure 16. Reset Timings............................................................... 43
Word/Byte Configuration (CIOf) ..............................................44
Figure 17. CIOf Timings for Read Operations................................ 44
Figure 18. CIOf Timings for Write Operations................................ 44
Erase and Program Operations ..............................................45
Figure 19. Program Operation Timings.......................................... 46
Figure 20. Accelerated Program Timing Diagram.......................... 46
Figure 21. Chip/Sector Erase Operation Timings .......................... 47
Figure 22. Back-to-back Read/Write Cycle Timings ...................... 48
Figure 23. Data# Polling Timings (During Embedded Algorithms). 48
Figure 24. Toggle Bit Timings (During Embedded Algorithms)...... 49
Figure 25. DQ2 vs. DQ6................................................................. 49
Temporary Sector Unprotect ..................................................50
Figure 26. Temporary Sector Unprotect Timing Diagram .............. 50
Figure 27. Sector/Sector Block Protect and
Unprotect Timing Diagram............................................................. 51
Alternate CE#f Controlled Erase and Program Operations ....52
Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 53
SRAM Read Cycle ..................................................................54
Figure 29. SRAM Read Cycle—Address Controlled...................... 54
Figure 30. SRAM Read Cycle........................................................ 55
SRAM Write Cycle ..................................................................56
Figure 31. SRAM Write Cycle—WE# Control................................ 56
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PDF描述
AM41DL6408H8H71IS Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVP00; No. of Contacts:6; Connector Shell Size:11; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM41DL6408H8H71IS 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM41DL6408H8H71IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM41DL6408H8H85IS 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM41DL6408H8H85IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
AM41LV3204M 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
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